STA308A13TR STMicroelectronics, STA308A13TR Datasheet - Page 21

• Manufacturer Part Number: STA308A13TR
• Description: IC AUDIO PROCESSOR DGTL 64-TQFP
• Manufacturer: STMicroelectronics
• Series: DDX™r
• Type: Audio Processorr

Specifications of STA308A13TR

• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Applications: Digital Audio
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STA308A
7.2
7.2.1
Register description
Configuration register A (0x00)
The DDX8000 supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4
kHz, 192 kHz, and 2.8224 MHz DSD. Therefore the internal clocks are:
"
"
"
The external clock frequency provided to the XTI pin must be a multiple of the input sample
frequency (fs). The relationship between the input clock and the input sample rate is
determined by both the MCSn and the IRn (input rate) register bits. The MCSn bits
determine the PLL factor generating the internal clock and the IRn bits determine the
oversampling ratio used internally.
Interpolation ratio select
The STA308A has variable interpolation (oversampling) settings such that internal
processing and DDX output rates remain consistent. The first processing block interpolates
by either 4 times, 2 times, or 1 time (pass-through).
The oversampling ratio of this interpolation is determined by the IR bits.
COS1
1
0
1
2
32, 44.1, 48
88.2, 96
176.4, 192
DSD
3
4
Bit
Bit
D7
65.536 MHz for 32 kHz
90.3168 MHz for 44.1 kHz, 88.2 kHz, 176.4 kHz, and DSD
98.304 MHz for 48 kHz, 96 kHz, and 192 kHz
Input sample rate
RW
RW
RW
RW
RW
RW
fs (kHz)
RW
COS0
0
D6
0
0
RST
1
1
0
RST
DSPB
0
IR0
IR1
D5
MCS0
MCS1
MCS2
00
01
10
11
Name
IR
Name
IR1
0
1XX
128 * fs
64 * fs
64 * fs
2 * fs
D4
Interpolation ratio select: selects internal
interpolation ratio based on input I
frequency
IR0
0
Master clock select: selects the ratio between the
input I
011
256 * fs
128 * fs
128 * fs
4 * fs
D3
2
S sample frequency and the input clock.
MCS2
0
MCS[2:0]
010
384 * fs
192 * fs
192 * fs
6 * fs
Description
D2
Description
MCS1
1
001
512 * fs
256 * fs
256 * fs
8 * fs
D1
2
S sample
MCS0
1
000
768 * fs
384 * fs
384 * fs
10 * fs
Registers
D0
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