STA308A13TR STMicroelectronics, STA308A13TR Datasheet - Page 15

• Manufacturer Part Number: STA308A13TR
• Description: IC AUDIO PROCESSOR DGTL 64-TQFP
• Manufacturer: STMicroelectronics
• Series: DDX™r
• Type: Audio Processorr

Specifications of STA308A13TR

• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Applications: Digital Audio
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STA308A
5
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.2
I
The STA308A supports the I
slave) and the output port SDA_OUT (slave to master).
This protocol defines any device that sends data on to the bus as a transmitter and any
device that reads the data as a receiver.
The device that controls the data transfer is known as the master and the other as the slave.
The master always starts the transfer and provides the serial clock for synchronization. The
STA308A is always a slave device in all of its communications.
Communication protocol
Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition
while the clock is high is used to identify a START or STOP condition.
Start condition
START is identified by a high to low transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A START condition must precede any command for
data transfer.
Stop condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal
SCL is stable in the high state. A STOP condition terminates communication between
STA308A and the bus master.
Data input
During the data input the STA308A samples the SDA signal on the rising edge of clock SCL.
For correct device operation the SDA signal must be stable during the rising edge of the
clock and the data can change only when the SCL line is low.
Device addressing
To start communication between the master and the Omega DDX core, the master must
initiate with a start condition. Following this, the master sends 8 bits onto the SDA line (MSB
first) corresponding to the device select address and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I
definition. In the STA308A the I
port configuration, 0x40 or 0100000x when SA = 0, and 0x42 or 0100001x when SA = 1.
The 8
for write mode. After a START condition the STA308A identifies on the bus the device
2
C bus operation
th
bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0
2
C protocol via the input ports SCL and SDA_IN (master to
2
C interface has two device addresses depending on the SA
I
2
C bus operation
2
C bus
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