ADUC834 Analog Devices, ADUC834 Datasheet - Page 49

• Manufacturer Part Number: ADUC834
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 62kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC834

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 4
• Other: PWM

8052 COMPATIBLE ON-CHIP PERIPHERALS
This section gives a brief overview of the various secondary
peripheral circuits that are also available to the user on-chip.
These remaining functions are mostly 8052 compatible (with a
few additional features) and are controlled via standard 8052
SFR bit definitions.
Parallel I/O
The ADuC834 uses four input/output ports to exchange data
with external devices. In addition to performing general-purpose
I/O, some ports are capable of external memory operations while
others are multiplexed with alternate functions for the peripheral
features on the device. In general, when a peripheral is enabled,
that pin may not be used as a general-purpose I/O pin.
Port 0
Port 0 is an 8-bit open-drain bidirectional I/O port that is directly
controlled via the Port 0 SFR. Port 0 is also the multiplexed low
order address and databus during accesses to external program
or data memory.
Figure 36 shows a typical bit latch and I/O buffer for a Port 0 port
pin. The bit latch (one bit in the port’s SFR) is represented as a
Type D flip-flop, which will clock in a value from the internal bus
in response to a “write to latch” signal from the CPU. The Q output
of the flip-flop is placed on the internal bus in response to a
“read latch” signal from the CPU. The level of the port pin itself
is placed on the internal bus in response to a “read pin” signal
from the CPU. Some instructions that read a port activate the
“read latch” signal, and others activate the “read pin” signal.
See the following Read-Modify-Write Instructions section for
more details.
As shown in Figure 36, the output drivers of Port 0 pins are
switchable to an internal ADDR and ADDR/DATA bus by an
internal CONTROL signal for use in external memory accesses.
During external memory accesses, the P0 SFR gets 1s written to
it (i.e., all of its bit latches become 1). When accessing external
memory, the CONTROL signal in Figure 36 goes high, enabling
push-pull operation of the output pin from the internal address
or databus (ADDR/DATA line). Therefore, no external pull-ups
are required on Port 0 in order for it to access external memory.
In general-purpose I/O port mode, Port 0 pins that have 1s
written to them via the Port 0 SFR will be configured as open-
drain and will therefore float. In this state, Port 0 pins can be
used as high impedance inputs. This is represented in Figure 36
by the NAND gate whose output remains high as long as the
CONTROL signal is low, thereby disabling the top FET. Exter-
nal pull-up resistors are therefore required when Port 0 pins are
used as general-purpose outputs. Port 0 pins with 0s written to
them will drive a logic low output voltage (V
capable of sinking 1.6 mA.
REV. A
INTERNAL
TO LATCH
LATCH
Figure 36. Port 0 Bit Latch and I/O Buffer
WRITE
READ
READ
BUS
PIN
LATCH
CL
D
Q
Q
ADDR/DATA
CONTROL
OL
DV
) and will be
DD
P0.x
PIN
–49–
Port 1
Port 1 is also an 8-bit port directly controlled via the P1 SFR.
The Port 1 pins are divided into two distinct pin groupings P1.0
to P1.1 and P1.2 to P1.7.
P1.0 and P1.1
P1.0 and P1.1 are bidirectional digital I/O pins with internal
pull-ups.
If P1.0 and P1.1 have 1s written to them via the P1 SFR, these
pins are pulled high by the internal pull-up resistors. In this state,
they can also be used as inputs. As input pins being externally
pulled low, they will source current because of the internal
pull-ups. With 0s written to them, both these pins will drive a
logic low output voltage (V
10 mA compared to the standard 1.6 mA sink capability on the
other port pins.
These pins also have various secondary functions described in
Table XXIV. The timer 2 alternate functions of P1.0 and P1.1
can only be activated if the corresponding bit latch in the P1
SFR contains a 1. Otherwise, the port pin is stuck at 0. In the
case of the PWM outputs at P1.0 and P1.1, the PWM outputs
will overwrite anything written to P1.0 or P1.1.
Pin
P1.0
P1.1
Figure 37 shows a typical bit latch and I/O buffer for a P1.0 or
P1.1 port pin. No external memory access is required from
either of these pins although internal pull-ups are present.
The internal pull-up consists of active circuitry as shown in
Figure 38. Whenever a P1.0 or P1.1 bit latch transitions from
low to high, Q1 in Figure 38 turns on for 2 oscillator periods to
quickly pull the pin to a logic high state. Once there, the weaker
Q3 turns on, thereby latching the pin to a logic high. If the pin
is momentarily pulled low externally, Q3 will turn off, but the
very weak Q2 will continue to source some current into the pin,
attempting to restore it to a logic high.
LATCH
Table XXIV. P1.0 and P1.1 Alternate Pin Functions
Figure 37. P1.0 and P1.1 Bit Latch and I/O Buffer
FROM
PORT
INTERNAL
TO LATCH
LATCH
WRITE
Q
READ
READ
Figure 38. Internal Pull-Up Configuration
BUS
Alternate Function
T2 (Timer/Counter 2 External Input)
PWM0 (PWM0 output at this pin)
T2EX (Timer/Counter 2 Capture/Reload Trigger)
PWM1 (PWM1 output at this pin)
PIN
DELAY
2 CLK
LATCH
CL
D
OUTPUT FUNCTION
Q
Q
ALTERNATE
OL
ALTERNATE
FUNCTION
) and will be capable of sinking
INPUT
Q4
Q1
DV
DD
DV
Q2
*SEE FIGURE 38
DV
FOR DETAILS OF
INTERNAL PULL-UP
DD
DD
INTERNAL
PULL-UP*
ADuC834
P1.x
Q3
PIN
DV
DD
Px.x
PIN