ADUC834 Analog Devices, ADUC834 Datasheet - Page 14

• Manufacturer Part Number: ADUC834
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 62kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC834

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 4
• Other: PWM

ADuC834
When accessing the internal XRAM, the P0 and P2 port pins,
as well as the RD and WR strobes, will not be output as per a
standard 8051 MOVX instruction. This allows the user to use
these port pins as standard I/O.
The upper 1792 bytes of the internal XRAM can be configured
to be used as an extended 11-bit stack pointer. By default, the
stack will operate exactly like an 8052 in that it will roll over from
FFH to 00H in the general-purpose RAM. On the ADuC834
however, it is possible (by setting CFG834.7) to enable the 11-bit
extended stack pointer. In this case, the stack will roll over from
FFH in RAM to 0100H in XRAM. The 11-bit stack pointer is
visible in the SP and SPH SFRs. The SP SFR is located at 81H
as with a standard 8052. The SPH SFR is located at B7H. The
3 LSBs of this SFR contain the three extra bits necessary to extend
the 8-bit stack pointer into an 11-bit stack pointer.
External Data Memory (External XRAM)
Just like a standard 8051 compatible core, the ADuC834 can
access external data memory using a MOVX instruction. The
MOVX instruction automatically outputs the various control
strobes required to access the data memory.
The ADuC834 however, can access up to 16 Mbytes of external
data memory. This is an enhancement of the 64 Kbytes external
data memory space available on a standard 8051 compatible core.
The external data memory is discussed in more detail in the
ADuC834 Hardware Design Considerations section.
Figure 4. Extended Stack Pointer Operation
CFG834.7 = 0
FFH
00H
ON-CHIP DATA
256 BYTES OF
(DATA +
STACK)
RAM
CFG834.7 = 1
07FFH
100H
00H
(DATA + STACK
ON-CHIP XRAM
ON-CHIP XRAM
FOR EXSP = 1,
FOR EXSP = 0)
(DATA ONLY)
UPPER 1792
DATA ONLY
LOWER 256
BYTES OF
BYTES OF
–14–
SPECIAL FUNCTION REGISTERS (SFRS)
The SFR space is mapped into the upper 128 bytes of internal
data memory space and accessed by direct addressing only. It
provides an interface between the CPU and all on-chip periph-
erals. A block diagram showing the programming model of the
ADuC834 via the SFR area is shown in Figure 5.
All registers, except the Program Counter (PC) and the four
general-purpose register banks, reside in the SFR area. The SFR
registers include control, configuration, and data registers that
provide an interface between the CPU and all on-chip peripherals.
Accumulator SFR (ACC)
ACC is the Accumulator Register and is used for math operations
including addition, subtraction, integer multiplication and division,
and Boolean bit manipulations. The mnemonics for accumulator-
specific instructions refer to the Accumulator as A.
B SFR (B)
The B Register is used with the ACC for multiplication and
division operations. For other instructions, it can be treated as
a general-purpose scratchpad register.
Data Pointer (DPTR)
The Data Pointer is made up of three 8-bit registers, named DPP
(page byte), DPH (high byte) and DPL (low byte). These are
used to provide memory addresses for internal and external
code access and external data access. It may be manipulated as
a 16-bit register (DPTR = DPH, DPL), although INC DPTR
instructions will automatically carry over to DPP, or as three
independent 8-bit registers (DPP, DPH, DPL).
The ADuC834 supports dual data pointers. Refer to the Dual
Data Pointer section in this data sheet.
62 KBYTE ELECTRICALLY
NONVOLATILE FLASH/EE
REPROGRAMMABLE
PROGRAM MEMORY
256 BYTES RAM
COMPATIBLE
2K XRAM
CORE
8051
Figure 5. Programming Model
FUNCTION
REGISTER
128-BYTE
SPECIAL
AREA
REPROGRAMMABLE
CURRENT SOURCES
OTHER ON-CHIP
FLASH/EE DATA
DUAL - ADCs
ELECTRICALLY
TEMP SENSOR
NONVOLATILE
PERIPHERALS
12-BIT DAC
SERIAL I/O
WDT, PSM
MEMORY
4 KBYTE
TIC, PLL
REV. A