ADUC834 Analog Devices, ADUC834 Datasheet - Page 28

• Manufacturer Part Number: ADUC834
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 62kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC834

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 4
• Other: PWM

ADuC834
ADC Chopping
Both ADCs on the ADuC834 implement a chopping scheme
whereby the ADC repeatedly reverses its inputs. The decimated
digital output words from the Sinc3 filters therefore have a
positive offset and negative offset term included.
As a result, a final summing stage is included in each ADC so
that each output word from the filter is summed and averaged
with the previous filter output to produce a new valid output
result to be written to the ADC data SFRs. In this way, while
the ADC throughput or update rate is as discussed earlier and
illustrated in Table VIII, the full settling time through the ADC
(or the time to a first conversion result), will actually be given
by 2
The chopping scheme incorporated in the ADuC834 ADC
results in excellent dc offset and offset drift specifications and is
extremely beneficial in applications where drift, noise rejection,
and optimum EMI rejection are important factors.
Calibration
The ADuC834 provides four calibration modes that can be
programmed via the mode bits in the ADCMODE SFR detailed
in Table V. In fact, every ADuC834 has already been factory
calibrated. The resultant Offset and Gain calibration coeffi-
cients for both the primary and auxiliary ADCs are stored
on-chip in manufacturing-specific Flash/EE memory locations.
At power-on or after reset, these factory calibration coefficients
are automatically downloaded to the calibration registers in the
ADuC834 SFR space. Each ADC (primary and auxiliary) has
dedicated calibration SFRs, these have been described earlier as
part of the general ADC SFR description. However, the factory
calibration values in the ADC calibration SFRs will be overwrit-
ten if any one of the four calibration options are initiated and
that ADC is enabled via the ADC enable bits in ADCMODE.
Even though an internal offset calibration mode is described
below, it should be recognized that both ADCs are chopped.
This chopping scheme inherently minimizes offset and means
that an internal offset calibration should never be required. Also,
because factory 5 V/25°C gain calibration coefficients are auto-
matically present at power-on, an internal full-scale calibration
will only be required if the part is being operated at 3 V or at
temperatures significantly different from 25°C.
The ADuC834 offers internal or system calibration facilities. For
full calibration to occur on the selected ADC, the calibration
logic must record the modulator output for two different input
conditions. These are zero-scale and full-scale points. These
points are derived by performing a conversion on the different
t
ADC
.
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input voltages provided to the input of the modulator during
calibration. The result of the zero-scale calibration conversion is
stored in the Offset Calibration Registers for the appropriate
ADC. The result of the full-scale calibration conversion is stored
in the Gain Calibration Registers for the appropriate ADC.
With these readings, the calibration logic can calculate the offset
and the gain slope for the input-to-output transfer function of
the converter.
During an internal zero-scale or full-scale calibration, the respective
zero-scale input and full-scale input are automatically connected
to the ADC input pins internally to the device. A system calibra-
tion, however, expects the system zero-scale and system full-scale
voltages to be applied to the external ADC pins before the cali-
bration mode is initiated. In this way, external ADC errors are
taken into account and minimized as a result of system calibration.
It should also be noted that to optimize calibration accuracy, all
ADuC834 ADC calibrations are carried out automatically at the
slowest update rate.
Internally in the ADuC834, the coefficients are normalized
before being used to scale the words coming out of the digital
filter. The offset calibration coefficient is subtracted from the
result prior to the multiplication by the gain coefficient.
From an operational point of view, a calibration should be
treated like another ADC conversion. A zero-scale calibration
(if required) should always be carried out before a full-scale
calibration. System software should monitor the relevant ADC
RDY0/1 bit in the ADCSTAT SFR to determine end of calibra-
tion via a polling sequence or interrupt driven routine.
NONVOLATILE FLASH/EE MEMORY
Flash/EE Memory Overview
The ADuC834 incorporates Flash/EE memory technology on-chip
to provide the user with nonvolatile, in-circuit reprogrammable,
code and data memory space. Flash/EE memory is a relatively
recent type of nonvolatile memory technology and is based on a
single transistor cell architecture. This technology is basically an
outgrowth of EPROM technology and was developed through
the late 1980s. Flash/EE memory takes the flexible in-circuit
reprogrammable features of EEPROM and combines them with
the space efficient/density features of EPROM. (See Figure 15).
Because Flash/EE technology is based on a single transistor cell
architecture, a Flash memory array, like EPROM, can be imple-
mented to achieve the space efficiencies or memory densities
required by a given design.
REV. A