AD5383 Analog Devices, AD5383 Datasheet - Page 36

• Manufacturer Part Number: AD5383
• Description: 32-Channel 12-Bit 3 V/5 V Single-Supply Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5383

• Resolution (bits): 12bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Par,Ser,SPI

AD5383
UTILIZING THE FIFO
The AD5383 FIFO mode optimizes total system update rates in
applications where a large number of channels need to be
updated. FIFO mode is only available when parallel interface
mode is selected. The FIFO EN pin is used to enable the FIFO.
The status of FIFO EN is sampled during the initialization
sequence. Therefore, the FIFO status can only be changed by
resetting the device. In a telescope that provides for the cancel-
lation of atmospheric distortion, for example, a large number of
channels need to be updated in a short period of time. In such
FIFO DATA LOAD
CHNLS 0-31
GROUP A
GROUP A
1.28μs
11.5μs
CHNLS 32-63
GROUP B
1.28μs
11.5μs
FIFO DATA LOAD
TIME FOR GROUP A
OUTPUT UPDATE
GROUP C
CHNLS
GROUP B
64-95
Figure 44. Using FIFO Mode 320 Channels Updated in Under 25 μs
TIME FOR GROUP B
OUTPUT UPDATE
GROUP D
CHNLS
96-127
TIME TO UPDATE 320 CHANNELS = 23μs
GROUP E
128-159
CHNLS
Rev. B | Page 36 of 40
GROUP F
160-191
CHNLS
systems, as many as 320 channels need to be updated within
25 μs to 30 μs. 320 channels require the use of 10 AD5383s.
With FIFO mode enabled, the data write cycle time is 40 ns;
therefore, each group consisting of 32 channels can be fully
loaded in 1.28 μs. In FIFO mode, a complete group of 32
channels updates in 11.5 μs. The time taken to update all 320
channels is 11.5 μs + 9 × 1.28 μs = 23 μs. Figure 44 shows the
FIFO operation scheme.
GROUP G
192-223
CHNLS
GROUP H
224-255
CHNLS
TIME FOR GROUP J
OUTPUT UPDATE
FIFO DATA LOAD
GROUP J
GROUP I
256-287
CHNLS
GROUP J
288-319
CHNLS
1.28μs
11.5μs