AD5383 Analog Devices, AD5383 Datasheet - Page 25

• Manufacturer Part Number: AD5383
• Description: 32-Channel 12-Bit 3 V/5 V Single-Supply Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5383

• Resolution (bits): 12bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Par,Ser,SPI

HARDWARE FUNCTIONS
RESET FUNCTION
Bringing the RESET line low resets the contents of all internal
registers to their power-on reset state. RESET is a negative edge-
sensitive input. The default corresponds to m at full scale and to
c at zero scale. The contents of the DAC registers are cleared,
setting V
The falling edge of RESET initiates the reset process; BUSY goes
low for the duration, returning high when RESET is complete.
While BUSY is low, all interfaces are disabled and all LDAC
pulses are ignored. When BUSY returns high, the part resumes
normal operation and the status of the RESET pin is ignored
until the next falling edge is detected.
ASYNCHRONOUS CLEAR FUNCTION
Bringing the CLR line low clears the contents of the DAC
registers to the data contained in the user-configurable CLR
register and sets V
be used in system calibration to load zero scale and full scale to
all channels. The execution time for a CLR is 32 μs.
BUSY AND LDAC FUNCTIONS
BUSY is a digital CMOS output that indicates the status of the
AD5383. The value of x2, the internal data loaded to the DAC
data register, is calculated each time the user writes new data to
the corresponding x1, c, or m registers. During the calculation
of x2, the BUSY output goes low. While BUSY is low, the user
can continue writing new data to the x1, m, or c registers, but
no DAC output updates can take place. The DAC outputs are
updated by taking the LDAC input low. If LDAC goes low while
BUSY is active, the LDAC event is stored and the DAC outputs
update immediately after BUSY goes high. The user may hold
the LDAC input permanently low, in which case the DAC
outputs update immediately after BUSY goes high. BUSY also
goes low during power-on reset and when a falling edge is
detected on the RESET pin. During this time, all interfaces are
disabled and any events on LDAC are ignored. The AD5383
contains an extra feature whereby a DAC register is not updated
unless its x2 register has been written to since the last time
LDAC was brought low. Normally, when LDAC is brought low,
the DAC registers are filled with the contents of the x2 registers.
However, the AD5383 will only update the DAC register if the
x2 data has changed, thereby removing unnecessary digital
crosstalk.
OUT
0 to V
OUT
OUT
31 to 0 V. This sequence takes 270 μs max.
0 to V
OUT
31 accordingly. This function can
Rev. B | Page 25 of 40
FIFO OPERATION IN PARALLEL MODE
The AD5383 contains a FIFO to optimize operation when
operating in parallel interface mode. The FIFO Enable (level
sensitive, active high) is used to enable the internal FIFO. When
connected to DV
user to write to the device at full speed. FIFO is only available in
parallel interface mode. The status of the FIFO EN pin is
sampled on power-up, and after a CLR or RESET , to determine
if the FIFO is enabled. In either serial or I
FIFO EN should be tied low. Up to 128 successive instructions
can be written to the FIFO at maximum speed in parallel mode.
When the FIFO is full, any further writes to the device are
ignored.
and non-FIFO mode in terms of channel update time.
also outlines digital loading time.
POWER-ON RESET
The AD5383 contains a power-on reset generator and state
machine. The power-on reset resets all registers to a predefined
state and configures the analog outputs as high impedance. The
BUSY pin goes low during the power-on reset sequencing,
preventing data writes to the device.
POWER-DOWN
The AD5383 contains a global power-down feature that puts all
channels into a low power mode and reduces the analog power
consumption to 2 μA maximum and digital power consumption
to 20 μA maximum. In power-down mode, the output amplifier
can be configured as high impedance output or provide a 100 kΩ
load to ground. The contents of all internal registers are
retained in power-down mode. When exiting power-down, the
settling time of the amplifier will elapse before the outputs settle
to their correct values.
25
20
15
10
5
0
Figure 29
1
Figure 29. Channel Update Rate (FIFO vs. Non-FIFO)
4
7
DD
shows a comparison between FIFO mode
, the internal FIFO is enabled, allowing the
10
13
NUMBER OF WRITES
16
(CHANNEL UPDATE TIME)
19
(DIGITAL LOADING TIME)
WITHOUT FIFO
22
(CHANNEL UPDATE TIME)
WITH FIFO
25
WITH FIFO
2
28
C interface modes,
31
34
AD5383
37
Figure 29
40