AD5384 Analog Devices, AD5384 Datasheet - Page 31

• Manufacturer Part Number: AD5384
• Description: 40-Channel, 3 V/5 V Single Supply,14-Bit, Serial Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5384

• Resolution (bits): 14bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser,SPI

MICROPROCESSOR INTERFACING
AD5384 to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is
configured for master mode (MSTR = 1), the Clock Polarity bit
(CPOL) = 0, and the Clock Phase bit (CPHA) = 1. The SPI is
configured by writing to the SPI control register (SPCR)—see
the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK
of the AD5384, the MOSI output drives the serial data line (D
of the AD5384, and the MISO input is driven from D
The SYNC signal is derived from a port line (PC7). When data
is being transmitted to the AD5384, the SYNC line is taken low
(PC7). Data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the 68HC11 is transmitted
in 8-bit bytes with only eight falling clock edges occurring in
the transmit cycle.
AD5384 to PIC16C6x/7x
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the Clock Polarity bit = 0. This is done by
writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 Microcontroller User Manual. In
this example I/O, port RA1 is being used to pulse SYNC and
enable the serial port of the AD5384. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, three consecutive read/write operations
could be needed, depending on the mode. Figure 33 shows the
connection diagram.
PIC16C6X/7X
MC68HC11
SDO/RC5
SCK/RC3
SDI/RC4
MISO
MOSI
SCK
PC7
RA1
Figure 33. AD5384-to-PIC16C6x/7x Interface
Figure 32. AD5384-toMC68HC11 Interface
DVDD
DVDD
SPI/I
RESET
SDO
DIN
SCLK
SYNC
SPI/I
RESET
SDO
DIN
SCLK
SYNC
AD5384
AD5384
2
2
C
C
OUT
.
Rev. A | Page 31 of 36
IN
)
AD5384 to 8051
The AD5384 requires a clock synchronized to the serial data.
The 8051 serial interface must therefore be operated in Mode 0.
In this mode, serial data enters and exits through RxD, and a
shift clock is output on TxD. Figure 34 shows how the 8051 is
connected to the AD5384. Because the AD5384 shifts data out
on the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. The AD5384
requires its data to be MSB first. Since the 8051 outputs the LSB
first, the transmit routine must take this into account.
AD5384 to ADSP-2101/ADSP-2103
Figure 35 shows a serial interface between the AD5384 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in SPORT transmit alternate framing mode.
The ADSP-2101/ADSP-2103 SPORT is programmed through
the SPORT control register and should be configured as follows:
internal clock operation, active low framing, and 16-bit word
length. Transmission is initiated by writing a word to the Tx
register after the SPORT has been enabled.
ADSP-2101/
ADSP-2103
8XC51
Figure 35. AD5384-to-ADSP-2101/ADSP-2103 Interface
SCK
RxD
P1.1
RFS
TxD
TFS
DR
DT
Figure 34. AD5384-to-8051 Interface
DVDD
DVDD
DVDD
SPI/I
RESET
SDO
DIN
SCLK
SYNC
SPI/I
RESET
SDO
DIN
SCLK
SYNC
AD5384
AD5384
2
2
C
C
AD5384