AD5384 Analog Devices, AD5384 Datasheet - Page 10

• Manufacturer Part Number: AD5384
• Description: 40-Channel, 3 V/5 V Single Supply,14-Bit, Serial Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5384

• Resolution (bits): 14bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser,SPI

AD5384
TIMING CHARACTERISTICS
SERIAL INTERFACE
DV
unless otherwise noted.
Table 7.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
1
2
3
4
5
6
7
7A
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Guaranteed by design and characterization, not production tested.
All input signals are specified with t
See
Standalone mode only.
Daisy-chain mode only.
4
4
4
4
5
5
5
DD
Figure 2 igure 3 Figure 5,
= 2.7 V to 5.5 V; AV
1, 2, 3
, F
,
Limit at T
33
13
13
13
13
33
10
50
5
4.5
30
670
20
20
100
0
100
8
20
12
20
5
8
20
DD
and
= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T
r
Figure 6
= t
f
= 5 ns (10% to 90% of DV
MIN
.
, T
MAX
TO OUTPUT PIN
Figure 2. Load Circuit for Digital Output Timing
DD
), and are timed from a voltage level of 1.2 V.
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
µs typ
ns min
µs max
ns max
ns min
ns min
ns min
Rev. A | Page 10 of 36
C
50pF
L
200µA
200µA
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24
Minimum SYNC low time
Minimum SYNC high time
Minimum SYNC high time in readback mode
Data setup time
Data hold time
24th SCLK falling edge to BUSY falling edge
BUSY pulse width low (single channel update)
24th SCLK falling edge to LDAC falling edge
LDAC pulse width low
BUSY rising edge to DAC output response time
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time boost mode off
CLR pulse width low
CLR pulse activation time
SCLK rising edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
th
I
I
OL
OH
SCLK falling edge to SYNC falling edge
V
V
OH
OL
(MAX)
(MIN) OR
MIN
to T
MAX
,