AD5384 Analog Devices, AD5384 Datasheet
AD5384
Specifications of AD5384
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AD5384 Summary of contents
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... REG INPUT DAC REG 7 REG REG REG 7 ×5 LDAC Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.326.8703 AD5384 REFGND REFOUT/REFIN SIGNAL GND (×5) 1.25V/2.5V REFERENCE 14 DAC 0 VOUT0 DAC 1 VOUT1 VOUT2 R VOUT3 R VOUT4 ...
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... Power-On Reset.......................................................................... 25 Power-Down ............................................................................... 25 Interfaces.......................................................................................... 26 DSP-, SPI-, Microwire-Compatible Serial Interfaces ............ Serial Interface ..................................................................... 28 Microprocessor Interfacing....................................................... 31 Application Information................................................................ 32 Power Supply Decoupling ......................................................... 32 Monitor Function....................................................................... 32 Toggle Mode Function............................................................... 32 Thermal Monitor Function....................................................... 33 AD5384 in a MEMS-Based Optical Switch ............................ 33 Optical Attenuators.................................................................... 34 Outline Dimensions ....................................................................... 35 Ordering Guide .......................................................................... 35 Rev Page ...
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... The AD5384 is a complete single-supply, 40-channel, 14-bit DAC available in a 100-lead CSPBGA package. All 40 channels have an on-chip output amplifier with rail-to-rail operation. The AD5384 includes an internal 1.25 V/2 ppm/°C reference, an on-chip channel monitor function that multiplexes the analog outputs to a common MON_OUT pin for external monitoring, and an output amplifier boost mode that allows the amplifier slew rate to be optimized ...
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... MΩ min Typically 100 MΩ ±1 µA max Typically ± min/max DD Enabled via CR10 in the AD5384 control register, CR12, selects the output voltage. 2.495/2.505 V min/max At ambient; CR12 = 1; optimized for 2.5 V operation 1.22/1.28 V min/max CR12 = 0 ±10 ppm/°C max Temperature range: +25° ...
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... AD5384-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C. 2 Accuracy guaranteed from OUT DD 3 Guaranteed by characterization, not production tested. 4 Default on the AD5384-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5384 control register; operating the AD5384-5 with a 1.25 V reference will lead to degraded accuracy specifications. 1 AD5384-5 Unit Test Conditions/Comments 0.4 V max DV DV – ...
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... Output Noise Spectral Density @ 1 kHz @ 10 kHz 1 Guaranteed by design and characterization, not production tested. 2 The slew rate can be programmed via the current boost control bit (CR11) in the AD5384 control register. AD5384-5 Unit Test Conditions/Comments Boost mode off, CR11 = 0 1/4 scale to 3/4 scale change settling to ±1 LSB 8 µ ...
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... AD5384-3 SPECIFICATIONS 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications unless otherwise noted. Table 5. Parameter ACCURACY Resolution 2 Relative Accuracy Differential Nonlinearity Zero-Scale Error Offset Error Offset Error TC Gain Error 3 Gain Temperature Coefficient 3 DC Crosstalk REFERENCE INPUT/OUTPUT 3 Reference Input ...
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... Accuracy guaranteed from OUT 3 Guaranteed by characterization, not production tested. 4 Default on the AD5384-3 is 1.25 V. Programmable to 2.5 V via CR12 in the AD5384 control register; operating the AD5384-3 with a 2.5 V reference will lead to degraded accuracy specifications and limited input code range. 1 AD5384-3 Unit 0.4 V max DV – ...
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... Output Noise Spectral Density @ 1 kHz @ 10 kHz 1 Guaranteed by design and characterization, not production tested. 2 The slew rate can be programmed via the current boost control bit (CR11 ) in the AD5384 control register 5.5 V; AGND = DGND = AD5384-3 Unit Test Conditions/Comments Boost mode off, CR11 = 0 1/4 scale to 3/4 scale change settling to ± ...
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... AD5384 TIMING CHARACTERISTICS SERIAL INTERFACE 3.6 V; AGND = DGND = 0 V; all specifications unless otherwise noted. Table Parameter Limit MIN ...
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... DB0 DB23 NOP CONDITION DB23 SELECTED REGISTER DATA CLOCKED OUT 24 DB0 DB23 INPUT WORD FOR DAC DB23 INPUT WORD FOR DAC N Rev Page AD5384 DB0 DB0 DB0 DB0 ...
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... AD5384 SERIAL INTERFACE 3.6 V; AGND = DGND = 0 V; all specifications unless otherwise noted. Table 8. 1 Parameter Limit MIN MAX F 400 SCL 100 300 ...
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... V DD other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute + 0 maximum rating conditions for extended periods may affect + 0 device reliability Rev Page AD5384 ...
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... AD5384 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 10. Pin Number and Name CSPBGA Ball CSPBGA Ball Number Name Number Name RESET A2 VOUT24 B10 VOUT22 A3 B11 NC CLR A4 SYNC B12 VOUT23 A5 SCLK C1 VOUT26 A6 DVDD1 C2 SIGNAL GND4 A7 DGND C11 C12 VOUT21 A9 DCEN D1 VOUT27 ...
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... Ground Reference Point for the Internal Reference. REFOUT/REFIN The AD5384 contains a common REFOUT/REFIN pin. The default for this pin is a reference input. When the internal reference is selected, this pin is the reference output. If the application requires an external reference, it can be applied to this pin. The internal reference is enabled/disabled via the control register. ...
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... AD5384 Mnemonic Function PD Power Down (Level Sensitive, Active High used to place the device in low power mode, where AI 2 µA and µA. In power-down mode, all internal analog circuitry is placed in low power mode, and the DD analog output is configured as a high impedance output or provides a 100 kΩ load to ground, depending on how the power-down mode is configured ...
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... Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) in the linear region of the transfer function, expressed in mV. Offset error is measured on the AD5384-5 with Code 32 loaded into the DAC register, and on the AD5384-3 with Code 64. Gain Error Gain Error is specified in the linear region of the output range ...
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... DD Rev Page REF T = 25° 4096 8192 12288 INPUT CODE Figure 11. Typical AD5384-3 INL Plot –5.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 –4.5 –3.5 –2.5 –1.5 –0.5 ...
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... V = DGND 25° 0.9 V OUT Rev Page 2.5V V OUT AV DD Figure 17. AD5384 Power-Up Transient AV DD REFIN = 2. 25°C A –2 – INL ERROR DISTRIBUTION (LSB) Figure 18. INL Distribution 2.5V REF 25°C OUT ...
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... A 4 3/4 SCALE FULL-SCALE 3 MIDSCALE ZERO-SCALE 1/4 SCALE –1 –40 –20 –10 –5 – CURRENT (mA) Figure 23. AD5384-3 Output Amplifier Source and Sink Capability 2.5V REF T = 25°C A 14ns/SAMPLE NUMBER 0 50 100 150 200 250 300 350 400 SAMPLE NUMBER Figure 24. Adjacent Channel DAC to DAC Crosstalk ...
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... DAC the 14-bit data-word written to the DAC input register the gain coefficient (default is 0x3FFE on the AD5384). The gain coefficient is written to the 13 most significant bits (DB13 to DB1) and the LSB (DB0 ...
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... ON-CHIP SPECIAL FUNCTION REGISTERS (SFR) The AD5384 contains a number of special function registers (SFRs), as outlined in Table 16. SFRs are addressed with REG1 = REG0 = 0 and are decoded using Address Bits A5 to A0. Table 16. SFR Register Functions (REG1 = 0, REG0 = 0) R ...
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... CR13 = 0: Amplifier output is 100 kΩ to ground. CR12: REF Select. This bit selects the operating internal reference for the AD5384. CR12 is programmed as follows: CR12 = 1: Internal reference is 2.5 V (AD5384-5 default), the recommended operating reference for AD5384-5. CR12 = 0: Internal reference is 1.25 V (AD5384-3 default), the recommended operating reference for AD5384-3. ...
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... AD5384 Table 19. AD5384 Channel Monitor Decoding REG1 REG0 ...
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... BUSY AND LDAC FUNCTIONS BUSY is a digital CMOS output that indicates the status of the AD5384. The value of x2, the internal data loaded to the DAC data register, is calculated each time the user writes new data to the corresponding x1, c ,or m registers. During the calculation of x2, the BUSY output goes low ...
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... DCEN—Selects Standalone Mode or Daisy-Chain Mode. SDO—Data Out Pin for Daisy-Chain Mode. Figure 3 and Figure 5 show the timing diagrams for a serial write to the AD5384 in standalone and in daisy-chain modes. The 24-bit data-word format for the serial interface is shown in Table 20. Table 20. 40-Channel, 14-Bit DAC Serial Input Register Configuration ...
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... AD5384, the following sequence should be followed. First, write 0x404XXX to the AD5384 input register. This configures the AD5384 for read mode with the m register of Channel 0 selected. Note that Data Bits DB13 to DB0 are don’t cares. Follow this with a second write, a NOP condition, 0x000000. ...
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... C-compatible 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the AD5384 and the master at rates up to 400 kHz. Figure 6 shows the 2-wire interface timing diagrams that incorporate three different modes of operation. ...
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... SDA REG1 REG0 MSB MOST SIGNIFICANT DATA BYTE AD1 AD0 R ACK BY MSB AD538x LSB MSB ACK BY AD538x 2 Figure 29. 4-Byte AD5384 Write Operation AD1 AD0 R ACK BY MSB AD538x LSB MSB ACK BY AD538x DATA FOR CHANNEL "N" ACK BY ...
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... AD5384 2-Byte Mode Following initialization of 2-byte mode, the user can update channels sequentially. The device address byte is required only once, and the pointer address pointer is configured for auto- increment or burst mode. The user must begin with an address byte ( 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low ...
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... AD5384, and the MISO input is driven from D The SYNC signal is derived from a port line (PC7). When data is being transmitted to the AD5384, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle ...
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... The printed circuit board on which the AD5384 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5384 system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only, a star ground point established as close to the device as possible ...
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... DACs that offer high channel density with 14-bit monotonic behavior. The 40-channel, 14-bit AD5384 DAC satisfies these requirements. In the circuit in Figure 38, the outputs of the AD5384 are amplified to achieve an output range 200 V, which is used to control actuators that determine the position of MEMS mirrors in an optical switch ...
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... PORTS PORTS OPTICAL SWITCH PHOTODIODES 11 ATTENUATOR 12 ATTENUATOR 1n–1 ATTENUATOR 1n ATTENUATOR N:1 MULTIPLEXER AD5384, 40-CHANNEL, 14-BIT DAC CONTROLLER 16-BIT ADC Figure 39. OADM Using the AD5384 as Part of an Optical Attenuator Rev Page DWDM OUT AWG FIBRE TIA/LOG AMP (AD8304/AD8305) ADG731 (40:1 MUX) AD7671 (0-5V, 1MSPS) ...
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... INDEX AREA BOTTOM F VIEW 0.80 BSC 1.11 1.01 0.91 0.12 MAX SEATING COPLANARITY PLANE Linearity Package Error (LSB) Description ±4 100-Lead CSPBGA ±4 100-Lead CSPBGA ±4 100-Lead CSPBGA ±4 100-Lead CSPBGA AD5384 Package Option BC-100-2 BC-100-2 BC-100-2 BC-100-2 ...
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... AD5384 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04652– ...