AD5384 Analog Devices, AD5384 Datasheet - Page 28

• Manufacturer Part Number: AD5384
• Description: 40-Channel, 3 V/5 V Single Supply,14-Bit, Serial Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5384

• Resolution (bits): 14bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser,SPI

AD5384
I
The AD5384 features an I
consisting of a serial data line (SDA) and a serial clock line
(SCL). SDA and SCL facilitate communication between the
AD5384 and the master at rates up to 400 kHz. Figure 6 shows
the 2-wire interface timing diagrams that incorporate three
different modes of operation.
Select I
The device is connected to this bus as slave devices, i.e., no
clock is generated by the AD5384. The AD5384 has a 7-bit slave
address 1010 1(AD1)(AD0). The 5 MSBs are hard coded, and
the two LSBs are determined by the state of the AD1 AD0 pins.
The ability to hardware-configure AD1 and AD0 allows four of
these devices to be configured on the bus.
I
One data bit is transferred during each SCL clock cycle. The
data on SDA must remain stable during the high period of the
SCL clock pulse. Changes in SDA while SCL is high are control
signals, which configure start and stop conditions. Both SDA
and SCL are pulled high by the external pull-up resistors when
the I
Start and Stop Conditions
A master device initiates communication by issuing a start
condition. A start condition is a high-to-low transition on SDA
with SCL high. A stop condition is a low-to-high transition on
SDA while SCL is high. A start condition from the master
signals the beginning of a transmission to the AD5384. The stop
condition frees the bus. If a repeated start condition (Sr) is
generated instead of a stop condition, the bus remains active.
Repeated START Conditions
A repeated start (Sr) condition may indicate a change of data
direction on the bus. Sr may be used when the bus master is
writing to several I
the bus.
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to any
8-bit data-word. ACK is always generated by the receiving
device. The AD5384 devices generate an ACK when receiving
an address or data by pulling SDA low during the ninth clock
period. Monitoring ACK allows detection of unsuccessful data
transfers. An unsuccessful data transfer occurs if a receiving
device is busy or if a system fault occurs. In the event of an
unsuccessful data transfer, the bus master should re-attempt
communication.
2
2
C Data Transfer
C SERIAL INTERFACE
2
C bus is not busy.
2
C mode by configuring the SPI/ I2C pin to a Logic 0.
2
C devices and wants to maintain control of
2
C-compatible 2-wire interface
Rev. A | Page 28 of 36
Slave Addresses
A bus master initiates communication with a slave device by
issuing a start condition followed by the 7-bit slave address.
When idle, the AD5384 waits for a start condition followed by
its slave address. The LSB of the address word is the Read/Write
(R/ W ) bit. The AD5384 devices are receive-only devices; when
communicating with these, R/ W = 0. After receiving the proper
address 1010 1(AD1)(AD0), the AD5384 issues an ACK by
pulling SDA low for one clock cycle.
The AD5384 has four different user programmable addresses
determined by the AD1 and AD0 bits.
Write Operation
There are three specific modes in which data can be written to
the AD5384 family of DACs.
4-Byte Mode
When writing to the AD5384 DACs, the user must begin with
an address byte (R/ W = 0), after which the DAC acknowledges
that it is prepared to receive data by pulling SDA low. The
address byte is followed by the pointer byte; this addresses the
specific channel in the DAC to be addressed and also is
acknowledged by the DAC. Two bytes of data are then written
to the DAC, as shown in Figure 29. A stop condition follows.
This lets the user update a single channel within the AD5384 at
any time and requires four bytes of data to be transferred from
the master.
3-Byte Mode
In 3-byte mode, the user can update more than one channel in a
write sequence without having to write the device address byte
each time. The device address byte is required only once; sub-
sequent channel updates require the pointer byte and the data
bytes. In 3-byte mode, the user begins with an address byte
(R/ W = 0), after which the DAC acknowledges that it is prepared
to receive data by pulling SDA low. The address byte is followed
by the pointer byte. This addresses the specific channel in the
DAC to be addressed and also is acknowledged by the DAC.
This is then followed by the two data bytes, REG1 and REG0,
which determine the register to be updated.
If a stop condition does not follow the data bytes, another
channel can be updated by sending a new pointer byte followed
by the data bytes. This mode requires only three bytes to be sent
to update any channel once the device is initially addressed, and
reduces the software overhead in updating the AD5384 channels.
A stop condition at any time exits this mode. Figure 30 shows a
typical configuration.