AD5384 Analog Devices, AD5384 Datasheet - Page 15

• Manufacturer Part Number: AD5384
• Description: 40-Channel, 3 V/5 V Single Supply,14-Bit, Serial Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5384

• Resolution (bits): 14bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser,SPI

Table 11. Pin Function Descriptions
Mnemonic
VOUTx
SIGNAL GND(1–5)
DAC GND(1–5)
AGND(1–5)
AVDD(1–5)
DGND
DVDD
REF GND
REFOUT/REFIN
VOUT39/MON_OUT
SYNC/AD0
DCEN/ AD1
SDO
LDAC
CLR
RESET
Function
Buffered Analog Outputs for Channel x. Each analog output is driven by a rail-to-rail output amplifier operating at a
gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω.
Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GND pins are tied together
internally and should be connected to the AGND plane as close as possible to the AD5384.
Each group of eight channels contains a DAC_GND pin. This is the ground reference point for the internal 14-bit DAC.
These pins shound be connected to the AGND plane.
Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be
connected externally to the AGND plane.
Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins are shorted internally and
should be decoupled with a 0.1 µF ceramic capacitor and a 10 µF tantalum capacitor. Operating range for the
AD5384-5 is 4.5 V to 5.5 V; operating range for the AD5384-3 is 2.7 V to 3.6 V.
Ground for All Digital Circuitry.
Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. It is recommended that these pins be decoupled
with 0.1 µF ceramic and 10 µF tantalum capacitors to DGND.
Ground Reference Point for the Internal Reference.
The AD5384 contains a common REFOUT/REFIN pin. The default for this pin is a reference input. When the internal
reference is selected, this pin is the reference output. If the application requires an external reference, it can be
applied to this pin. The internal reference is enabled/disabled via the control register.
This pin has a dual function. It acts a a buffered output for Channel 39 in default mode. But when the monitor
function is enabled, this pin acts as the output of a 39-to-1 channel multiplexer that can be programmed to multiplex
one of Channels 0 to 38 to the MON_OUT pin. The MON_OUT pin output impedance typically is 500 Ω and is
intended to drive a high input impedance like that exhibited by SAR ADC inputs.
Serial Interface Mode. This is the frame synchronization input signal for the serial clocks before the addressed register
is updated.
I
for the device on the I
Multifunction Pin. In serial interface mode, this pin acts as a daisy-chain enable in SPI mode and as a hardware
address pin in I
Serial Interface. Daisy-chain select input (level sensitive, active high). When high, this signal is used in conjunction
with SPI/ I
I
for this device on the I
Serial Data Output in Serial Interface Mode. Three-stateable CMOS output. SDO can be used for daisy-chaining a
number of devices together. Data is clocked out on SDO on the rising edge of SCLK, and is valid on the falling edge of
SCLK.
Digital CMOS Output. BUSY goes low during internal calculations of the data (x2) loaded to the DAC data register.
During this time, the user can continue writing new data to the x1, c, and m registers, but no further updates to the
DAC registers and DAC outputs can take place. If LDAC is taken low while BUSY is low, this event is stored. BUSY also
goes low during power-on reset, and when the BUSY pin is low. During this time, the interface is disabled and any
events on LDAC are ignored. A CLR operation also brings BUSY low.
Load DAC Logic Input (Active Low). If LDAC is taken low while BUSY is inactive (high), the contents of the input
registers are transferred to the DAC registers, and the DAC outputs are updated. If LDAC is taken low while BUSY is
active and internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when
BUSY goes inactive. However, any events on LDAC during power-on reset or on RESET are ignored.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is activated, all channels are updated
with the data in the CLR code register. BUSY is low for a duration of 35 µs while all channels are being updated with
the CLR code.
Asynchronous Digital Reset Input (Falling Edge Sensitive). The function of this pin is equivalent to that of the power-
on reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m,
c, and x2 registers to their default power-on values. This sequence typically takes 270 µs. The falling edge of RESET
initiates the RESET process and BUSY goes low for the duration, returning high when RESET is complete. While BUSY
is low, all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal
operation and the status of the RESET pin is ignored until the next falling edge is detected.
2
2
C Mode. This pin acts as a hardware address pin used in conjunction with AD1 to determine the software address
C Mode. This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address
2
C high to enable the SPI serial interface daisy-chain mode.
2
C mode.
2
2
C bus.
C bus.
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AD5384