AD9789 Analog Devices, AD9789 Datasheet - Page 57

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Finally, when measuring performance for CMTS and other
digital TV applications, it is advantageous to insert a 1 dB,
1.2 GHz Chebyshev low-pass filter between the DAC and the
transformer to better control the impedance seen at the DAC
core. This helps to decrease the folded back harmonics for
higher frequency outputs. The optimal transformer for CMTS
measurements is the JTX-2-10T, which consists of a balun and
center-tapped transformer in a single package. This output stage
is shown in Figure 112.
Traces from the DAC to the transformer should be 50 Ω imped-
ance to ground each in Figure 110 and Figure 112 and 25 Ω to
ground each in Figure 111 to avoid unnecessary parasitics.
CLOCKING THE AD9789
To provide the required signal swing for the internal clock
receiver of the AD9789, it is necessary to use an external clock
buffer chip to drive the CLKP and CLKN inputs. These high
level, high slew rate signals should not be routed any distance
on a PCB. The recommended clock buffer for this application
providing 1.9 V out of each side into a 50 Ω load terminated
to V
is the ADCLK914. This ultrafast clock buffer is capable of
IOUTN
IOUTP
CC
70Ω
(3.3 V) for a total differential swing of 3.8 V.
Figure 112. Recommended Transformer Output Stage
PSTRNKPE4117
2
90Ω
3
GND
J3
4
1
5
90Ω
4.7pF
4.7pF
for CMTS Measurements
R15
49.9Ω
GND
0.01µF
0.01µF
5.6nH
5.6nH
C81
C82
2.2pF
GND
Figure 114. ADCLK914/AD9789 Interface Circuit for Use with a Lab Generator
1
2
3
4
GND
D
D
NC
NC
JTX-2-10T
16 15 14 13
5 6 7 8
C83
0.01µF
GND
NC
NC
Q
Q
U3
ADCLK914
12
11
10
9
Rev. A | Page 57 of 76
VCC33
VCC33
The buffer, in turn, can be easily driven from lower level signals
such as CML or attenuated PECL that might be encountered on
a PCB. This buffer also provides very low, 100 fs added random
jitter, which is important to obtain the optimal ac performance
from the AD9789. A functional block diagram of the ADCLK914
is shown in Figure 113. Figure 114 shows the recommended
schematic for the ADCLK914/AD9789 interface. Refer to the
ADCLK914 data sheet for more information. Any time that the
noise floor from the DAC cannot meet the specifications in this
data sheet, the clock should be examined.
The internal 50 Ω resistors shown at the ADCLK914 inputs are
rated to carry currents from PECL or CML drivers. The V
can be connected to V
V
common-mode input range of the ADCLK914 does not include
LVDS voltage levels, so ac coupling is required in that case.
REF
, or it can be left floating depending on the source. The
V
GND
C31
0.1µF
C0402
REF
V
ADCLK914 SUPPLY DECOUPLING
D
D
T
Figure 113. ADCLK914 Functional Block Diagram
R13
49.9Ω
50Ω
GND
C32
0.01µF
C0402
50Ω
R14
49.9Ω
CC
V
, a PECL current sink, or the internal
CC
GND
C33
0.1µF
C0402
V
VCC33
EE
C0803H50
C0803H50
2400pF
2400pF
ADCLK914
C102
C99
GND
C34
0.01µF
C0402
VCC33
R17
100Ω
R0402
Q
Q
CLKP
CLKN
50Ω
AD9789
50Ω
T
pin