AD9789 Analog Devices, AD9789 Datasheet - Page 50

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9789
LVDS DDR
LVDS SDR
Retimer and Latency Look-Up Tables
In practice, the retimer and latency parameters can be reduced
to a single verified and guaranteed table that provides delays at
optimum sample points from 0 to over 100 DAC clocks. The
sampling points for LVDS DDR, LVDS SDR, and CMOS inter-
face modes are given in Figure 99 for delay = 0. The number
scale above the DCO signal in Figure 99 corresponds to the
delay value in DAC clock cycles in Table 66 and Table 67.
The delay of the pins should be taken into account. This delay is
800 ps for the output delay and 800 ps for the input delay, for a
total of 1.6 ns. This delay is included in the following formulas.
See Table 66 for a complete set of recommended retimer settings
for all delay values. Note: for LVDS DDR, zero (0) measured delay
results in a retimer setting of 20, while for .LVDS SDR or CMOS,
the zero(0) delay corresponds to a retimer setting of 12 at f
2.4 GHz.
To use Table 66 and Table 67, probe the FS, DCO, and data
input signals at the AD9789. While viewing these signals on an
oscilloscope, measure the delay between the rising edge of FS
and the start of the first data sample and add 1.6 ns from the
delay of the pins to this value. Normalize this total delay to one
DAC clock period. The optimum sampling point in number of
DAC clock cycles, which corresponds to the delay number in
Table 66 and Table 67, can be found from this measured value
for each interface mode.
CMOS
DCO
FS
SAMPLE
SAMPLE
0 1 2 3 4 5 6 7 8
SAMPLE
SAMPLE
SAMPLE
SAMPLE
16
SAMPLE
SAMPLE
Figure 99. Sampling Points at Delay = 0
24
DAC
Rev. A | Page 50 of 76
=
SAMPLE
SAMPLE
32
For LVDS DDR,
For LVDS SDR,
For CMOS,
For a maximum valid sampling window, the sampling point
should be fine-tuned based on the data input setup and hold
times. If the setup and hold times are symmetric about the
DCO edge, choosing a sampling point at the center of the data
window results in the maximum valid sampling window. For
more information on the input data setup and hold times, refer
to the CMOS Interface Timing section or the LVDS Interface
Timing section.
The LAT, SNC, and DSC values for the optimal sampling point in
Table 66 or Table 67 should be written to the LTNCY[2:0] bits in
Register 0x21[2:0], the SNCPHZ[3:0] bits in Register 0x23[3:0],
and the DSCPHZ[3:0] bits in Register 0x23[7:4], respectively.
SAMPLE
SAMPLE
Delay
40
Delay
Delay
OPTIMAL
OPTIMAL
OPTIMAL
SAMPLE
SAMPLE
=
48
=
=
Delay
Delay
Delay
MEASURED
MEASURED
MEASURED
t
t
t
DCO
SAMPLE
SAMPLE
DCO
DCO
56
/
/
16
/
16
16
+
+
+
1
1
1
6 .
6 .
6 .
ns
ns
ns
SAMPLE
SAMPLE
+
+
+
64
16
8
8
SAMPLE
SAMPLE
72