AD9789 Analog Devices, AD9789 Datasheet - Page 45

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

DIGITAL INTERFACE MODES
The AD9789 can be configured for two main digital interface
modes of operation:
•
•
In channelizer mode (Register 0x20[3] = 0), the interface can be
configured for 4- to 32-bit bus widths and can accept up to four
channels of complex data. Any of the signal processing blocks in
the digital datapath can be used. The maximum baud rate
supported in channelizer mode is f
In QDUC mode (Register 0x20[3] = 1), the interface is fixed at
a 32-bit bus width and one channel of complex data. The available
signal processing methods are interpolation (16× to 512×), rate
conversion (0.5 to 1.0), and complex modulation. The maximum
baud rate supported in QDUC mode is f
In both channelizer and QDUC modes, the input data bus
can be configured to accept LVDS or CMOS data via the
CMOS_BUS pin (L14). If CMOS_BUS is pulled to 3.3 V, the
data bus is configured to accept CMOS inputs (D[31:0], P0,
and P1). If CMOS_BUS is pulled to 0 V, the bus is configured
to accept LVDS inputs (D[15:0]P, D[15:0]N, PARP, and PARN).
Two output signals are used to source data into the AD9789.
The first is the data clock output signal (DCO), which is
provided to clock data from the digital data source. DCO is a
divided-down version of DACCLK. The second is the frame sync
signal (FS), which is provided to request a new data-word. The
average frequency of the FS signal is equal to the symbol rate or
baud rate of the data. As with the input data bus, the DCO and
FS signals can be configured as LVDS or CMOS outputs via the
CMOS_CTRL pin (M14). If CMOS_CTRL is pulled to 3.3 V,
DCO and FS are output as CMOS signals on the P14 and N14
pins (CMOS_DCO and CMOS_FS), respectively. If CMOS_CTRL
is pulled to 0 V, DCO and FS are output as LVDS signals on the
N13, P13, L13, and M13 pins (DCOP, DCON, FSP, and FSN),
respectively.
Channelizer Mode
In channelizer mode, the digital interface has programmable
bus width, data width, and data format. The bus width, which is
the physical width of the digital data bus at the input of the
AD9789, can be set to a 4-, 8-, 16-, or 32-bit wide interface. The
data width, which is the internal width of the data at the input
to the digital datapath, can be set to an 8-bit or 16-bit word. The
data format can be programmed for real or complex data. A list
of supported interface modes is shown in Table 55.
Channelizer mode
Quadrature digital upconverter (QDUC ) mode
DAC
/48.
DAC
/16.
Rev. A | Page 45 of 76
DCO
Table 55. Interface Configurations Supported
in Channelizer Mode
First Input
Block Enabled
QAM Encoder
SRRC Filter
Interpolation
Filter
If the QAM encoder is the first block enabled in the datapath,
the data width should be set to an 8-bit word and real data
format. If the SRRC filter is the first block enabled in the
datapath, the data width should be set to an 8-bit word and
complex data format. If both the QAM encoder and the SRRC
filters are bypassed, the data width should be set to a 16-bit
word and complex data format.
Pin Mapping in Channelizer Mode
In CMOS mode (CMOS_BUS and CMOS_CTRL pins = 3.3 V),
the various interface width options are mapped to the AD9789
input pins as shown in Table 56.
Table 56. CMOS Pin Assignments for Various Interface Widths
Interface Width
4 bits
8 bits
16 bits
32 bits
FS
P0
P1
16 TO 31
0 TO 15
CMOS
CMOS
LVDS
LVDS
FALL
RISE
CLK
CTL
Bus Width
Reg. 0x21[6:5]
32 bits
16 bits
8 bits
4 bits
32 bits
16 bits
8 bits
4 bits
32 bits
16 bits
8 bits
Figure 92. Channelizer Mode
Pin Assignments
D[3:0]
D[7:0]
D[15:0]
D[31:0]
16 TO 1024
f
32 BITS
32 BITS
32 BITS
32 BITS
DAC
UP TO
UP TO
UP TO
UP TO
DATA-
DATA-
DATA-
DATA-
PATH
PATH
PATH
PATH
0
1
2
3
Data Width
Reg. 0x21[4]
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
16 bits
8 bits
16 bits
16 bits
32
SCALE
SUM
f
DAC
BUSWDTH[1:0]
00
01
10
11
16
Data Format
Reg. 0x21[3]
Real
Real
Real
Real
Complex
Complex
Complex
Complex
Complex
Complex
Complex
AD9789
f
C
f
f
DAC/2
BPF
BPF
= 0 TO
DAC
f
C