AD9789 Analog Devices, AD9789 Datasheet - Page 40

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9789
Table 50. QAM Mapper Input and Output Range vs. Mode
ITU-T J.83
Annex
B
B
A
A
A and C
A and C
A and C
1
Each constellation point corresponds to an I and Q coordinate
pair, as shown in Figure 74. In the figure, two symbols are high-
lighted in a 64-QAM constellation: I = 14, Q = 14 (Pair 1) and
I = 6, Q = −10 (Pair 2).
To represent the I and Q coordinate points, 5-bit, twos com-
plement numbers are used. For example, an input of 011101
into the QAM encoder maps to the I = 6, Q = −10 position of
the QAM-64 constellation and results in output samples of
I = 00110, Q = 10110.
X = don’t care.
–14
16
8
(I and Q Paths Are Identical So Only One Is Shown)
Figure 75. QAM Mapper and SRRC Filter Detail
–10
INSCALE
MAPPER
QAM
X
Figure 74. I and Q Symbol Mapping
–6
Description
DOCSIS 64-QAM
DOCSIS 256-QAM
DVB-C 16-QAM
DVB-C 32-QAM
DVB-C 64-QAM
DVB-C 128-QAM
DVB-C 256-QAM
Unused
16
5
BYPASS
QAM
–2
–10
–14
14
10
–2
–6
6
2
Q
16
5
2
SYMBOL I = 6, Q = –10
I = 00110, Q = 10110
SRRC
2
SYMBOL I = 14, Q = 14
I = 01110, Q = 01110
6
16
10
BYPASS
SRRC
010
011
SPI Register 0x07,
MAPPING[2:0] Bits
000
001
100
101
110
111
14
16
I
Rev. A | Page 40 of 76
Input Scalar
The input scalar block is active only when the QAM mapper
is bypassed. The value of INSCALE[7:0] is programmed in
Register 0x09[7:0]. The scale factor applied to the input data
is calculated as follows:
This factor provides a scaling range of the input data from 0 to
7.96875 in steps of 0.03125. The default value of 0x20 provides a
scale factor of 1. As shown in Figure 76, the output of the input
scalar block is rounded to the nearest 16-bit value. If the output
exceeds the maximum or minimum value, it is clipped to either
positive or negative full scale (0x7FFF or 0x8000).
SRRC Filter
The square root raised cosine (SRRC) filter performs a 2×
interpolation and filtering operation on the input data. The
SRRC filter has a pass band, transition band, and stop band
requirement as per the DOCSIS, Euro-DOCSIS, and DVB-C
standards.
To cover all the standards, the value of alpha can be set to 0.12,
0.13, 0.15, or 0.18. This value is programmed in Register 0x07[5:4].
The frequency, f
The response of the SRRC filter is illustrated in Figure 77.
The SRRC filter accepts only five bits at its input and can be
bypassed (Register 0x06[6]). If the SRRC filter is the first block
enabled in the datapath, these five bits are the five MSBs of the
8-bit data-word.
ScaleFacto 
r
Bit Range
at Output
−14 to +14
−15 to +15
−15 to +15
−15 to +15
−14 to +14
−11 to +11
−15 to +15
Figure 76. Input Scalar Block Diagram
N
, is determined by the input data baud rate.
INSCALE[7:
INSCALE
8
32
SATURATE
ROUND
0]
Input Bits
B7 B6 B5 B4 B3 B2 B1 B0
X X C5 C4 C3 C2 C1 C0
C7 C6 C5 C4 C3 C2 C1 C0
X X X X C3 C2 C1 C0
X X X C4 C3 C2 C1 C0
X X C5 C4 C3 C2 C1 C0
X C6 C5 C4 C3 C2 C1 C0
C7 C6 C5 C4 C3 C2 C1 C0
1