AD9789 Analog Devices, AD9789 Datasheet - Page 46

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9789
In LVDS mode, the various interface width options are mapped
to the AD9789 input pins as shown in Table 57. When the inter-
face width is set to 32 bits in LVDS mode, the interface becomes
double data rate (DDR). In DDR mode, the first 16 bits are
sampled on the rising edge of the data sampling clock (DSC,
which is synchronous to DCO), and the second 16 bits are
sampled on the falling edge of DSC. All other interface widths
are single data rate (SDR), where the input data is sampled on
the falling edge of DSC.
Table 57. LVDS Pin Assignments for Various Interface Widths
Interface Width
4 bits
8 bits
16 bits
32 bits
In nibble or byte loading, the most significant nibble or byte
should be loaded first. Data for Channel 0 should be loaded first
followed by Channel 1, Channel 2, and Channel 3. In complex
data format, the in-phase part should be loaded before the
quadrature part of the data-word. The data bus is LSB justified
when the data for each channel is assembled internally. A few
examples of how the interface maps for different configurations
follow. For more information on how a particular configuration
is mapped, see the Channelizer Mode Pin Mapping for CMOS
and LVDS section.
Example 1
For a CMOS interface with a 32-bit bus width, 8-bit data width,
real data format, and four channels enabled, the data in Table 58
is expected on the input port after data is requested.
Table 58. CMOS Pin Mapping for Bus Width = 32 Bits,
Data Width = 8 Bits, Data Format = Real, Four Channels
DCO
1
1
Example 2
For a CMOS interface with a 32-bit bus width, 8-bit data width,
complex data format, and four channels enabled, the data in
Table 59 is expected on the input port after data is requested.
Table 59. CMOS Pin Mapping for Bus Width = 32 Bits,
Data Width = 8 Bits, Data Format = Complex, Four Channels
DCO
1
2
1
R represents the real data loaded to a given channel; the channel number
follows R.
I represents the in-phase term and Q represents the quadrature term of the
complex data loaded to a given channel; the channel number follows I or Q.
D[31:24]
R3
D[31:24]
Q1
Q3
Pin Assignments
D[3:0]P, D[3:0]N
D[7:0]P, D[7:0]N
D[15:0]P, D[15:0]N
D[15:0]P, D[15:0]N rising
edge and falling edge
D[23:16]
R2
D[23:16]
I1
I3
D[15:8]
R1
D[15:8]
Q0
Q2
BUSWDTH[1:0]
00
01
10
11
D[7:0]
R0
D[7:0]
I0
I2
1
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1
Example 3
For an LVDS interface with a 16-bit bus width, 8-bit data width,
complex data format, and four channels enabled, the data in
Table 60 is expected on the input port after data is requested.
Table 60. LVDS Pin Mapping for Bus Width = 16 Bits,
Data Width = 8 Bits, Data Format = Complex, Four Channels
DCO
1
2
3
4
1
Example 4
For an LVDS interface with a 32-bit bus width, 8-bit data width,
complex data format, and four channels enabled, the data in
Table 61 is expected on the input port after data is requested.
Table 61. LVDS Pin Mapping for Bus Width = 32 Bits,
Data Width = 8 Bits, Data Format = Complex, Four Channels
DCO
1 rise
1 fall
2 rise
2 fall
1
2
DCO and FS Rates in Channelizer Mode
The DCO signal is a data clock output provided to clock data
from the digital data source. The DCO is a divided version of
the DAC clock. The FS signal is an output provided to request a
new data-word. The average frequency of the FS signal (f
exactly equal to the symbol rate or baud rate (f
FS is intended as a request line; timing should be taken from the
DCO. The frequencies of the DCO signal (f
(f
following two equations:
where:
I is the interpolation factor, which can range from 1 to 64.
P/Q is the rate conversion factor (0.5 to 1.0, inclusive).
N is a programmable DCO divide factor set using the
DCODIV[2:0] bits in Register 0x22[6:4].
Set DCODIV[2:0] to 1, 2, or 4. A value of 0 disables the DCO.
A DCODIV value of 3 is not functional. The frequency of the
DSC signal is always equal to DCO.
“Rise” means that the data is sourced on the rising edge of DCOx; “fall” means
I represents the in-phase term and Q represents the quadrature term of the
complex data loaded to a given channel; the channel number follows I or Q.
I represents the in-phase term and Q represents the quadrature term of the
complex data loaded to a given channel; the channel number follows I or Q.
that the data is sourced on the falling edge of DCOx.
BAUD
2
f
), and the DAC clock (f
DCO
f
DAC
= f
=
DAC
I
×
/(16 × N)
D[15:8]P, D[15:8]N
Q0
Q1
Q2
Q3
D[15:8]P, D[15:8]N
Q0
Q1
Q2
Q3
Q
P
×
16
×
f
BAUD
DAC
) are related as shown by the
D[7:0]P, D[7:0]N
I0
I1
I2
I3
D[7:0]P, D[7:0]N
I0
I1
I2
I3
DCO
BAUD
), the baud rate
) of the data.
FS
) is
(1)
(2)
1
1