AD9122 Analog Devices, AD9122 Datasheet - Page 50

• Manufacturer Part Number: AD9122
• Manufacturer: Analog Devices

Specifications of AD9122

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9122
DEVICE POWER MANAGEMENT
POWER DISSIPATION
The AD9122 has four supply rails: AVDD33, IOVDD, DVDD18,
and CVDD18.
The AVDD33 supply powers the DAC core circuitry. The power
dissipation of the AVDD33 supply rail is independent of the digital
operating mode and sample rate. The current drawn from the
AVDD33 supply rail is typically 55 mA (182 mW) when the full-
scale current of the I and Q DACs is set to the nominal value of
20 mA. Changing the full-scale current directly affects the supply
current drawn from the AVDD33 rail. For example, if the full-scale
current of the I DAC and the Q DAC is changed to 10 mA, the
AVDD33 supply current drops by 20 mA to 35 mA.
The IOVDD voltage supplies the serial port I/O pins, the RESET
pin, and the IRQ pin. The voltage applied to the IOVDD pin can
range from 1.8 V to 3.3 V. The current drawn by the IOVDD
supply pin is typically 3 mA.
The DVDD18 supply powers all of the digital signal processing
blocks of the device. The power consumption from this supply
is a function of which digital blocks are enabled and the frequency
at which the device is operating.
The CVDD18 supply powers the clock receiver and clock distri-
bution circuitry. The power consumption from this supply varies
directly with the operating frequency of the device. CVDD18 also
powers the PLL. The power dissipation of the PLL is typically
80 mW when enabled.
Figure 76 through Figure 80 show the power dissipation of
the AD9122 under a variety of operating conditions. All of
the graphs were taken with data being supplied to both the I
and Q DACs. The power consumption of the device does not
vary significantly with changes in the coarse modulation mode
selected or the analog output frequency. Figure 76 through
Figure 80 show the total power dissipation, as well as the power
dissipation of the DVDD18 and CVDD18 supplies.
Maximum power dissipation can be estimated to be 20% higher
than the typical power dissipation.
Rev. B | Page 50 of 60
Figure 76. Total Power Dissipation vs. f
Figure 77. DVDD18 Power Dissipation vs. f
1700
1500
1300
1100
1200
1000
Figure 78. CVDD18 Power Dissipation vs. f
900
700
500
300
100
800
600
400
200
250
200
150
100
50
0
0
0
0
0
1× INTERPOLATION
2× INTERPOLATION
4× INTERPOLATION
8× INTERPOLATION
1× INTERPOLATION
2× INTERPOLATION
4× INTERPOLATION
8× INTERPOLATION
1× INTERPOLATION
2× INTERPOLATION
4× INTERPOLATION
8× INTERPOLATION
50
50
50
100
100
100
or Inverse Sinc
or Inverse Sinc
f
f
f
DATA
DATA
DATA
150
150
150
(MHz)
(MHz)
(MHz)
DATA
200
200
200
Without PLL, Fine NCO,
DATA
DATA
Without Fine NCO
with PLL Disabled
250
250
250
300
300
300