AD9122 Analog Devices, AD9122 Datasheet - Page 18

• Manufacturer Part Number: AD9122
• Manufacturer: Analog Devices

Specifications of AD9122

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9122
DIFFERENCES BETWEEN AD9122R1 AND AD9122R2
The AD9122 underwent a die revision in early 2010, which
incremented the die revision from R1 to R2. The following list
explains the differences between the revisions.
•
•
•
•
•
IOVDD supply voltage range.
For the AD9122R1, the valid operational voltage range
for IOVDD is 1.8 V to 2.5 V ± 10%. For the AD9122R2,
the valid operational voltage range for IOVDD is 1.8 V
to 3.3 V ± 10%.
Reduction in spurs level variation.
The AD9122R1 has variation in the f
between device startups. The AD9122R2 has a consistent
and lower f
a spur level variation between power cycles of about 5 dB
if the PLL is enabled.)
DCI delay feature added.
The AD9122R2 has a programmable delay associated with
the DCI signal. There are four programmable delay options.
The 00 setting gives the minimum delay and leaves the
timing unchanged from the AD9122R1. Additional delay
can be added to improve timing margins in some systems.
The resulting timing options are shown in Table 13.
Power-down mode power consumption increase.
The maximum power-down mode power consumption
of the R1 devices is 9.8 mW. This power consumption
increased to 18.8 mW in the R2 devices.
Configuration register map changes.
Register 0x0B, Bit 5:
Register 0x16, Bits[1:0]:
Register 0x7F:
AD9122R1
AD9122R2
when the PLL is enabled.
AD9122R1
AD9122R2
signal (00 = minimum delay, 11 = maximum delay).
AD9122R1
AD9122R2
DATA
± f
Enable VCO
Inactive bit. The VCO is now enabled
Unused
These bits control the delay of the DCI
Version ID = 0x04
Version ID = 0x0C
OUT
spur level. (The AD9122R2 still has
DATA
± f
OUT
spur level
Rev. B | Page 18 of 60
DEVICE MARKING OF AD9122R1 AND AD9122R2
Revision 1 devices are marked as shown in Figure 36. Revision 1
devices with TxDAC® as the top line have date codes earlier than
#1001. Revision 1 devices with AD80255 as the top line have date
codes of #1001 or later.
Revision 2 devices are marked as shown in Figure 37. Revision 2
devices have TxDAC® as the top line and date codes of #1001 or
later.
DATE CODE
Figure 36. Revision 1 Silicon, AD9122BCPZ Marking
Figure 37. Revision 2 Silicon, AD9122BCPZ Marking
DATE CODE
TxDAC
AD9122BCPZ
#0935
1688587.1
KOREA
®
TxDAC
AD9122BCPZ
#1021
1688782.1
KOREA
®
AD80255
AD9122BCPZ
#1001
1688586.1
KOREA