AD9122 Analog Devices, AD9122 Datasheet - Page 34

• Manufacturer Part Number: AD9122
• Manufacturer: Analog Devices

Specifications of AD9122

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9122
Resetting the FIFO
When the AD9122 is powered on, the FIFO depth is unknown.
To avoid a concurrent read and write to the same FIFO address
and to ensure a fixed pipeline delay, it is important to reset the
FIFO pointers to known states. The FIFO pointers can be initial-
ized in two ways: via a write sequence to the serial port or by
strobing the FRAME input. There are two types of FIFO resets:
a relative reset and an absolute reset. A relative reset enforces a
defined FIFO depth. An absolute reset enforces a particular write
pointer value when the reset is initiated. A serial port initiated
FIFO reset is always a relative reset. A FRAME strobe initiated
reset can be either a relative or an absolute reset.
If the FRAME differential inputs are not used for FIFO reset
or for framing the word width, they must be tied to logic low.
FRAMEP must be tied to DVSS, and FRAMEN must be tied
to DVDD18 to avoid accidental reset of the FIFO due to noise.
The operation of the FRAME initiated FIFO reset depends on
the synchronization mode chosen.
•
•
For more information about the synchronization function, see
the Multichip Synchronization section.
A summary of the synchronization modes and the types of
FIFO reset used is provided in Table 14.
Table 14. Summary of FIFO Resets
FIFO Reset Signal
Serial Port
FRAME
Serial Port Initiated FIFO Reset
A serial port initiated FIFO reset can be issued in any synchro-
nization mode and always results in a relative FIFO reset. To
initialize the FIFO data level through the serial port, Bit 1 of
Register 0x18 should be toggled from 0 to 1 and back. When the
write to this register is complete, the FIFO data level is initialized.
When the initialization is triggered, the next time that the read
pointer becomes 0, the write pointer is set to the value of the FIFO
start level variable (Register 0x17, Bits[2:0]) upon initialization.
By default, this value is 4, but it can be programmed to a value
from 0 to 7. It is recommended that a value of 5 (0x05) be pro-
grammed in Register 0x17.
When synchronization is disabled or when it is configured
for data rate mode synchronization, the FRAME strobe
initiates a relative FIFO reset. The reference point of the
relative reset is the position of the read pointer.
When FIFO mode synchronization is chosen, the FRAME
strobe initiates an absolute FIFO reset.
Disabled
Relative
Relative
Synchronization Mode
Data Rate
Relative
Relative
FIFO Reset
Absolute
Relative
Rev. B | Page 34 of 60
The recommended procedure for a serial port FIFO data level
initialization is as follows:
1.
2.
3.
4.
5.
6.
7.
8.
FRAME Initiated Relative FIFO Reset
The primary function of the FRAME input is to indicate to
which DAC the input data is written. Another function of the
FRAME input is to initialize the FIFO data level value. This is
done by asserting the FRAME signal high for at least the time
interval required to load complete data to the I and Q DACs.
This corresponds to one DCI period in word mode, two DCI
periods in byte mode, and four DCI periods in nibble mode.
To initiate a relative FIFO reset with the FRAME signal, the
device must be configured in data rate mode (Register 0x10,
Bit 6 = 1). When FRAME is asserted in data rate mode, the
write pointer is set to 4 by default (or to the FIFO start level)
the next time that the read pointer becomes 0 (see Figure 48).
POINTER
POINTER
FRAME
WRITE
READ
Program Register 0x17 to 0x05.
Request FIFO level reset by setting Register 0x18, Bit 1, to 1.
Verify that the part acknowledges the request by ensuring
that Register 0x18, Bit 2, is set to 1.
Remove the request by setting Register 0x18, Bit 1, to 0.
Verify that the part drops the acknowledge signal by
ensuring that Register 0x18, Bit 2, is set to 0.
Read back Register 0x19 to verify that the pointer spacing
is set to 3 (0x07) or 4 (0x0F).
If the readback of Register 0x19 shows a pointer spacing of
2 (0x03), increment Register 0x17 to a spacing of 0x06 and
repeat Step 2 through Step 5. Read back Register 0x19 again
to verify that the pointer spacing is now set to 3 (0x07).
If the readback of Register 0x19 shows a pointer spacing of
5 (0x1F) after Step 6, decrement Register 0x17 to a spacing
of 0x04 and repeat Step 2 through Step 5. Read back
Register 0x19 again to verify that the pointer spacing is
now set to 4 (0x0F).
Figure 48. FRAME Input vs. Write Pointer Value, Data Rate Mode
0
3
1
4
2
5
6
3
FIFO WRITE RESETS
7
4
5
0
6
1
7
2
3
0
4
1
2
5
3
6