AD5737 Analog Devices, AD5737 Datasheet - Page 6

• Manufacturer Part Number: AD5737
• Description: Quad Channel, 12-Bit, Serial Input, 4-20mA Output DAC with Dynamic Power Control and HART Connectivity
• Manufacturer: Analog Devices

Specifications of AD5737

• Resolution (bits): 12bit
• Dac Settling Time: 15µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Ser,SPI

AD5737
AC PERFORMANCE CHARACTERISTICS
AV
REFIN = 5 V; R
Table 2.
Parameter
DYNAMIC PERFORMANCE, CURRENT
1
TIMING CHARACTERISTICS
AV
REFIN = 5 V; R
Table 3.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Guaranteed by design and characterization; not production tested.
Guaranteed by design and characterization; not production tested.
All input signals are specified with t
See Figure 3, Figure 4, Figure 5, and Figure 6.
This specification applies if LDAC is held low during the write cycle; otherwise, see t
4
OUTPUT
Output Current Settling Time
Output Noise (0.1 Hz to 10 Hz
Output Noise Spectral Density
DD
DD
Bandwidth)
= V
= V
BOOST_x
BOOST_x
1, 2, 3
1
L
L
= 15 V; DV
= 15 V; DV
= 300 Ω; all specifications T
= 300 Ω; all specifications T
Limit at T
33
13
13
13
13
198
5
5
20
5
10
500
See Table 2
10
5
40
21
5
500
800
20
5
DD
DD
MIN
RISE
= 2.7 V to 5.5 V; AV
= 2.7 V to 5.5 V; AV
, T
= t
MAX
FALL
= 5 ns (10% to 90% of DV
Min
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs min
μs min
ns min
ns max
μs max
ns min
μs max
ns max
μs min
μs min
ns min
ns min
μs min
μs min
See Test Conditions/Comments
MIN
MIN
to T
to T
CC
CC
MAX
MAX
= 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSW
= 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSW
Typ
15
0.15
0.5
, unless otherwise noted.
, unless otherwise noted.
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24th/32nd SCLK falling edge to SYNC rising edge (see
SYNC high time
Data setup time
Data hold time
SYNC rising edge to LDAC falling edge (all DACs updated or any channel has
digital slew rate control enabled)
SYNC rising edge to LDAC falling edge (single DAC updated)
LDAC pulse width low
LDAC falling edge to DAC output response time
DAC output settling time
CLEAR high time
CLEAR activation time
SCLK rising edge to SDO valid
SYNC rising edge to DAC output response time (LDAC = 0)
All DACs updated
Single DAC updated
LDAC falling edge to SYNC rising edge
RESET pulse width
SYNC high to next SYNC low (digital slew rate control enabled)
All DACs updated
Single DAC updated
DD
) and timed from a voltage level of 1.2 V.
Rev. A | Page 6 of 44
Max
9
.
Unit
μs
ms
LSB p-p
nA/√Hz
Test Conditions/Comments
To 0.1% FSR, 0 mA to 24 mA range
For settling times when using the dc-to-dc con-
verter, see Figure 25, Figure 26, and Figure 27
12-bit LSB, 0 mA to 24 mA range
Measured at 10 kHz, midscale output, 0 mA
to 24 mA range
Figure 53
)
Data Sheet
x
x
= 0 V;
= 0 V;