AD5737 Analog Devices, AD5737 Datasheet - Page 34

• Manufacturer Part Number: AD5737
• Description: Quad Channel, 12-Bit, Serial Input, 4-20mA Output DAC with Dynamic Power Control and HART Connectivity
• Manufacturer: Analog Devices

Specifications of AD5737

• Resolution (bits): 12bit
• Dac Settling Time: 15µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Ser,SPI

AD5737
HART CONNECTIVITY
The
output channel. A HART signal can be coupled into these pins.
The HART signal appears on the corresponding current output,
if the output is enabled. Table 33 shows the recommended input
voltages for the HART signal at the CHART pin. If these voltages
are used, the current output should meet the HART amplitude
specifications.
Table 33. CHART Input Voltage to HART Output Current
R
Internal R
External R
Figure 54 shows the recommended circuit for attenuating and
coupling the HART signal. A minimum capacitance of C1 + C2
is required to ensure that the 1.2 kHz and 2.2 kHz HART
frequencies are not significantly attenuated at the output. The
recommended values are C1 = 22 nF and C2 = 47 nF.
Digitally controlling the slew rate of the output is necessary to
meet the analog rate of change requirements for HART.
DIGITAL SLEW RATE CONTROL
The digital slew rate control feature of the
user to control the rate at which the output value changes. With
the slew rate control feature disabled, the output value changes
at a rate limited by the output drive circuitry and the attached
load. To reduce the slew rate, the user can enable the digital slew
rate control feature using the SREN bit of the slew rate control
register (see Table 28).
When slew rate control is enabled, the output, instead of slewing
directly between two values, steps digitally at a rate defined by
the SR_CLOCK and SR_STEP parameters. These parameters
are accessible via the slew rate control register (see Table 28).
•
•
Together, these parameters define the rate of change of the
output value. Table 34 and Table 35 list the range of values for
the SR_CLOCK and SR_STEP parameters, respectively.
SET
AD5737
SR_CLOCK defines the rate at which the digital slew is
updated; for example, if the selected update rate is 8 kHz,
the output is updated every 125 μs.
SR_STEP defines by how much the output value changes
at each update.
SET
SET
has four CHART pins, one corresponding to each
CHART Input Voltage
150 mV p-p
170 mV p-p
HART MODEM
Figure 54. Coupling the HART Signal
OUTPUT
C1
C2
CHARTx
Current Output (HART)
1 mA p-p
1 mA p-p
AD5737
allows the
Rev. A | Page 34 of 44
Table 34. Slew Rate Update Clock Options
SR_CLOCK
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
Table 35. Slew Rate Step Size Options
SR_STEP
000
001
010
011
100
101
110
111
The following equation describes the slew rate as a function of
the step size, the update clock frequency, and the LSB size.
where:
Slew Rate is expressed in seconds.
Output Change is expressed in amperes.
The update clock frequency for any given value is the same for
all output ranges. The step size, however, varies across output
ranges for a given value of step size because the LSB size is
different for each output range.
These clock frequencies are divided down from the 13 MHz internal
oscillator (see Table 1, Figure 45, and Figure 46).
Slew
Step
Size
Rate
×
=
Update
Update Clock Frequency
64 kHz
32 kHz
16 kHz
8 kHz
4 kHz
2 kHz
1 kHz
500 Hz
250 Hz
125 Hz
64 Hz
32 Hz
16 Hz
8 Hz
4 Hz
0.5 Hz
Step Size (LSB)
1
2
4
16
32
64
128
256
Output
Clock
Change
Frequency
×
LSB
1
Data Sheet
Size