AD5737 Analog Devices, AD5737 Datasheet - Page 30

• Manufacturer Part Number: AD5737
• Description: Quad Channel, 12-Bit, Serial Input, 4-20mA Output DAC with Dynamic Power Control and HART Connectivity
• Manufacturer: Analog Devices

Specifications of AD5737

• Resolution (bits): 12bit
• Dac Settling Time: 15µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Ser,SPI

AD5737
Slew Rate Control Register
This register is used to program the slew rate control for the
selected DAC channel. The slew rate control is enabled/disabled
and programmed on a per-channel basis. See Table 28 and the
Digital Slew Rate Control section for more information.
READBACK OPERATION
Readback mode is invoked by setting the R/ W bit = 1 in the serial
input register write. See
back operation. The DUT_AD1 and DUT_AD0 bits, in association
with Bits[RD4:RD0], select the register to be read (see
The remaining data bits in the write sequence are don’t care bits.
During the next SPI transfer, the data that appears on the SDO
output contains the data from the previously addressed register
Table 28. Programming the Slew Rate Control Register
D15
0
1
Table 29. Input Shift Register for a Read Operation
MSB
D23
R/W
1
Table 30. Read Addresses (Bits[RD4:RD0])
RD4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
X = don’t care.
X = don’t care.
RD3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
D22
DUT_AD1
D14
0
Table 29
RD2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
for the bits associated with a read-
D21
DUT_AD0
D13
0
0
0
0
1
1
RD1
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
D20
RD4
Table 30
D12
SREN
RD0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Rev. A | Page 30 of 44
).
D19
RD3
Function
Read DAC A data register
Read DAC B data register
Read DAC C data register
Read DAC D data register
Read DAC A control register
Read DAC B control register
Read DAC C control register
Read DAC D control register
Read DAC A gain register
Read DAC B gain register
Read DAC C gain register
Read DAC D gain register
Read DAC A offset register
Read DAC B offset register
Read DAC C offset register
Read DAC D offset register
Read DAC A clear code register
Read DAC B clear code register
Read DAC C clear code register
Read DAC D clear code register
Read DAC A slew rate control register
Read DAC B slew rate control register
Read DAC C slew rate control register
Read DAC D slew rate control register
Read status register
Read main control register
Read dc-to-dc control register
(see Figure 4). This second SPI transfer should be either a request
to read another register on a third data transfer or a no operation
command. The no operation command for DUT Address 00 is
0x1CE000; for other DUT addresses, Bits[D22:D21] are set
accordingly.
Readback Example
To read back the gain register of
implement the following sequence:
1.
2.
D11 to D7
X
1
D18
RD2
Write 0xA80000 to the input register to configure Device
Address 1 for read mode with the gain register of Channel A
selected. The data bits, D15 to D0, are don’t care bits.
Execute another read command or a no operation com-
mand (0x3CE000). During this command, the data from
the Channel A gain register is clocked out on the SDO line.
D17
RD1
D6 to D3
SR_CLOCK
AD5737
D16
RD0
Device 1, Channel A,
D2 to D0
SR_STEP
Data Sheet
D15 to D0
X
1
LSB