AD539JD Analog Devices Inc, AD539JD Datasheet - Page 12

IC MULT/DIV DUAL CH LIN 16-CDIP

AD539JD

Manufacturer Part Number
AD539JD
Description
IC MULT/DIV DUAL CH LIN 16-CDIP
Manufacturer
Analog Devices Inc
Datasheets

Specifications of AD539JD

Rohs Status
RoHS non-compliant
Function
Analog Multiplier/Divider
Number Of Bits/stages
2
Package / Case
16-CDIP (0.300", 7.62mm)
Number Of Elements
2
Output Type
Single
Power Supply Requirement
Dual
Single Supply Voltage (typ)
Not RequiredV
Single Supply Voltage (min)
Not RequiredV
Single Supply Voltage (max)
Not RequiredV
Dual Supply Voltage (typ)
±5/±9/±12V
Dual Supply Voltage (min)
±4.5V
Dual Supply Voltage (max)
±15V
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
16
Package Type
SBCDIP
Lead Free Status / RoHS Status
Not Compliant

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APPLICATIONS INFORMATION
BASIC MULTIPLIER CONNECTIONS
Figure 20 shows the connections for the standard dual-channel
multiplier, using op amps to provide useful output power and
the AD539 feedback resistors to achieve accurate scaling. The
transfer function for each channel is
where the inputs and outputs are expressed in volts (see the
Transfer Function section).
At the nominal full-scale inputs of V
full-scale outputs are ±6 V. Depending on the choice of op amp,
their supply voltages may need to be about 2 V more than the
peak output. Thus, supplies of at least ±8 V are required; the
AD539 can share these supplies. Higher outputs are possible if
V
respectively, when the peak output is ±13.4 V. This requires
operating the op amps at supplies of ±15 V. Under these condi-
tions, it is advisable to reduce the supplies to the AD539 to
±7.5 V to limit its power dissipation; however, with some form
of heat-sinking, it is permissible to operate the AD539 directly
from ±15 V supplies.
NOTES
1. ALL DECOUPLING CAPACITORS ARE 0.47µF CERAMIC.
Viewed as a voltage-controlled amplifier, the decibel gain is simply
where V
V
In many ac applications, the output offset voltage (for V
or V
nated using the offset nulling method recommended for the
particular op amp, with V
At small values of V
degrades the gain/loss accuracy. For example, a ±1 mV offset
uncertainty causes the nominal 40 dB attenuation at V
0.01 V to range from 39.2 dB to 40.9 dB. Figure 4 shows the
maximum gain error boundaries based on the guaranteed
control channel offset voltages of ±2 mV for the AD539K and
±4 mV for the AD539J. These curves include all scaling errors
AD539
V
V
V
Y1
Y2
X
X
X
and V
= 3.162 V, 0 dB at V
Y
V
C
G = 20 log V
C
= 0 V) is not a major concern; however, it can be elimi-
W
= 3nF
+V
–V
= −V
X
Y
S
S
is expressed in volts. This results in a gain of 10 dB at
are driven to their peak values of +3.2 V and ±4.2 V,
1
2
3
4
5
6
7
8
X
Figure 20. Standard Dual-Channel Multiplier
V
V
HF COMP
V
+V
–V
V
INPUT
COMMON
OUTPUT
COMMON
X
Y1
Y2
Y
S
S
X
(16-Lead SBDIP and PDIP Shown)
AD539
X
COMMON
, the offset voltage of the control channel
X
OUTPUT
OUTPUT
BASE
CHAN1
CHAN2
= 1 V, −20 dB at V
X
= V
W2
W1
Z2
Z1
16
15
14
13
12
11
10
Y
9
= 0 V.
NC
NC
X
C
C
= 3 V and V
F
F
–V
–V
X
= 0.1 V, and so on.
S
S
+V
S
Y
= ±2 V, the
X
X
=
= 0 V
V
–V
V
–V
W1
W2
X
X
Rev. B | Page 12 of 20
V
V
=
=
Y1
Y2
and apply to all configurations using the internal feedback
resistors (W1 and W2 or, alternatively, Z1 and Z2).
Distortion is a function of the signal input level (V
control input (V
in practice, the op amp generates most of the distortion at frequen-
cies above 100 kHz. Figure 5 shows typical results at f = 10 kHz
as a function of V
In some cases, it may be desirable to alter the scaling. This can
be achieved in several ways. One option is to use both the Z and
W feedback resistors (see Figure 18) in parallel, in which case
V
must be held at ±3 V FS (±6.75 peak), for example, to allow the use
of reduced supply voltages for the op amps. Alternatively, the
gain can be doubled by connecting both channels in parallel and
using only a single feedback resistor, in which case V
and the full-scale output is ±12 V. Another option is to insert a
resistor in series with the control channel input, permitting the
use of a large (for example, 0 V to 10 V) control voltage. A
disadvantage of this scheme is the need to adjust this resistor to
accommodate the tolerance of the nominal 500 Ω input resistance
at Pin 1, V
attenuated to permit operation at higher values of V
case it may often be possible to partially compensate for the
response roll-off of the op amp by adding a capacitor across the
upper arm of this attenuator.
Signal Channel AC and Transient Response
The HF response is dependent almost entirely on the op amp.
Note that the noise gain for the op amp in Figure 20 is determined
by the value of the feedback resistor (6 kΩ) and the 1.25 kΩ
control-bias resistors (see Figure 18). Op amps with provision
for external frequency compensation should be compensated
for a closed-loop gain of 6.
The layout of the circuit components is very important if low
feedthrough and flat response at low values of V
maintained (see the General Recommendations section).
For wide bandwidth applications requiring an output voltage
swing greater than ±1 V, the LH0032 hybrid op amp is recom-
mended. Figure 6 shows the HF response of the circuit of Figure 20
using this amplifier with V
as shown in Table 4. C
V; the −3 dB bandwidth exceeds 25 MHz. The effect of signal
feedthrough on the response becomes apparent at V
The minimum feedthrough results when V
negative to ensure that the residual control channel offset is
exceeded and the dc gain is reliably zero. Measurements show
that the feedthrough can be held to −90 dB relative to full
output at low frequencies and to −60 dB up to 20 MHz with
careful board layout. The corresponding pulse response is
shown in Figure 7 for a signal input of V
values of V
W
= −V
X
V
X
. The signal channel inputs can also be resistively
X
Y
(3 V and 0.1 V).
/2. This may be preferable where the output swing
X
). It is also a function of frequency, although
X
with V
F
was adjusted for 1 dB peaking at V
Y
Y
= 0.5 V rms and 1.5 V rms.
= 1 V rms and other conditions
Y
of ±1 V and two
X
is taken slightly
X
is to be
W
Y
) and the
Y
= −2V
X
, in which
= 0.01 V.
X
X
Y
= 1
Y

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