AD7760 Analog Devices, AD7760 Datasheet - Page 6

• Manufacturer Part Number: AD7760
• Description: 2.5 MSPS, 24-Bit, 100 dB Sigma-Delta ADC with On-Chip Buffer
• Manufacturer: Analog Devices

Specifications of AD7760

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 40MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 4 V p-p,6.5 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP

AD7760
TIMING SPECIFICATIONS
AV
Table 3.
Parameter
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
MCLK
ICLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
t
When ICLK = MCLK, DRDY pulse width depends on the mark-space ratio of applied MCLK.
Valid when using the modulator output mode with CDIV = 1.
See the Modulator Data Output Mode section for timing diagrams.
Valid when using the modulator output mode with CDIV = 0.
2
1, 2
ICLK
2
3, 4
4, 5
4, 5
3, 4
DD
= 1/f
1 = DV
ICLK
.
DD
= V
Limit at T
1
40
500
20
0.5 × t
10
3
(0.5 × t
t
t
3
11
0.5 × t
0.5 × t
(0.5 × t
23
19
11
4 × t
4 × t
5
0
23
19
ICLK
ICLK
DRIVE
ICLK
ICLK
= 2.5 V, AV
ICLK
ICLK
ICLK
ICLK
ICLK
) + 16 ns
) + 16 ns
MIN
, T
MAX
DD
2 = AV
DD
Unit
MHz min
MHz max
kHz min
MHz max
typ
ns min
ns min
max
min
min
ns min
ns max
typ
typ
max
ns min
ns min
ns max
min
min
ns min
ns min
ns min
ns min
3 = AV
DD
4 = 5 V, T
Rev. A | Page 6 of 36
Description
Applied master clock frequency
Internal modulator clock derived from MCLK
DRDY pulse width
DRDY falling edge to CS falling edge
RD/WR setup time to CS falling edge
Data access time
CS low read pulse width
CS high pulse width between reads
RD/WR hold time to CS rising edge
Bus relinquish time
DRDY high period
DRDY low period
Data access time
Data valid prior to DRDY rising edge
Data valid after DRDY rising edge
Bus relinquish time
CS low write pulse width
CS high period between address and data
Data setup time
Data hold time
Data valid prior to MCLK falling edge while DRDY is logic low
Data valid after MCLK falling edge while DRDY is logic low
A
= 25°C, normal mode, unless otherwise noted.