AD7760 Analog Devices, AD7760 Datasheet
AD7760
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AD7760 Summary of contents
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... V differential biased around a common mode This common-mode biasing can be achieved using the on-chip differential amplifier, further reducing the external signal conditioning requirements. The AD7760 is available in an exposed paddle, 64-lead TQFP and is specified over the industrial temperature range from −40°C to +85°C. Table 1. Related Devices Part No ...
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... Modulator Inputs........................................................................ 19 Modulator Data Output Scaling ............................................... 19 Modulator Data Output Mode Interface ..................................... 20 Clock Divide-by-1 Mode ( CDIV = 1) ..................................... 20 Clock Divide-by-2 Mode ( CDIV = 0) ..................................... 20 Using the AD7760 in Modulator Output Mode..................... 21 AD7760 Interface............................................................................ 22 Reading Data............................................................................... 22 Reading Status and Other Registers......................................... 22 Sharing the Parallel Bus ............................................................. 22 Synchronization.......................................................................... 22 Writing to the AD7760 ...
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... Added Figure 41 Through Figure 47 ............................................19 Added Modulator Data Output Mode Interface Section...........20 Changes to Reading Data Section.................................................22 Added Synchronization Section....................................................22 Changes to Clocking the AD7760 Section...................................24 Added Buffering the MCLK Signal Section.................................24 Added MCLK Jitter Requirements Heading ...............................24 Changes to Driving the AD7760 Section.....................................26 Changes to Figure 51 ......................................................................26 Added Figure 52 ...
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... AD7760 SPECIFICATIONS 2 DRIVE DD the on-chip amplifier with components as shown in Table 8, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Decimate by 256 Dynamic Range 2 Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) Decimate by 32 Dynamic Range ...
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... Current scales with ICLK frequency. See the Typical Performance Characteristics section. 4 Although the AD7760 can function with an MCLK amplitude of less than 5 V, this is the recommended amplitude to achieve the performance as stated. 5 Tested using the minimum V voltage of 1.65 V with a 400 μA load current. ...
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... AD7760 TIMING SPECIFICATIONS 2 DRIVE DD Table 3. Parameter Limit MIN MAX f 1 MCLK 40 f 500 ICLK 0.5 × ICLK (0.5 × ICLK ICLK ICLK 0.5 × t ...
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... TIMING DIAGRAMS DRDY CS RD/WR D[0:15] CS RD/ D[0:15 DATA MSW Figure 2. Filtered Output—Parallel Interface Timing Diagram REGISTER ADDRESS Figure 3. AD7760 Register Write Rev Page AD7760 LSW + STATUS REGISTER DATA ...
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... AD7760 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Parameters GND GND GND GND DRIVE – to GND A+, V A− to GND Digital Input Voltage to GND MCLK to MCLKGND V to GND 3 REF+ AGND to DGND ...
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... TOP VIEW (Not to Scale REF Figure 4. 64-Lead TQFP Pin Configuration Rev Page AD7760 48 DB12 DB13 47 46 DB14 DB15 DRIVE DGND 43 42 DGND ...
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... Read/Write Input. This pin, in conjunction with the chip select pin, is used to read and write data to and from the AD7760. If this pin is low when CS is low, a read takes place. If this pin is high when CS is low, a write occurs. See the Modulator Data Output Mode and AD7760 Interface sections for more details. ...
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... The AD7760 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies ...
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... AD7760 TYPICAL PERFORMANCE CHARACTERISTICS 2 DRIVE DD FFTs are generated from 65,536 samples using a 7-term Blackman-Harris window. 0 –25 –50 –75 –100 –125 –150 –175 –200 0 4000 8000 12000 FREQUENCY (Hz) Figure 5. Normal Mode FFT, 1 kHz, −0.5 dB Input Tone, 256× Decimation 0 – ...
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... Figure 15. Low Power FFT, 100 kHz, −6 dB Input Tone, 8× Decimation 0 –25 –50 –75 –100 –125 –150 –175 –200 1000 1250 0 Figure 16. Low Power FFT, 1 MHz, −0.5 dB Input Tone, 8× Decimation Rev Page AD7760 250 500 750 1000 1250 FREQUENCY (kHz) 250 500 750 1000 1250 FREQUENCY (kHz) 250 500 ...
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... AD7760 0 –25 –50 –75 –100 –125 –150 –175 –200 0 250 500 750 FREQUENCY (kHz) Figure 17. Normal Mode FFT, 1 MHz, −6 dB Input Tone, 8× Decimation 0 TONE A: 999.75kHz –25 TONE B: 1.00025MHz –50 –75 –100 –125 –150 –175 –200 0 250 500 750 FREQUENCY (kHz) Figure 18. Normal Mode IMD, 1 MHz Center Frequency, 8× ...
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... Figure 28. Low Power SNR vs. Decimation Rate, 1 kHz Input Tone Rev Page TONE A: 999.75kHz TONE B: 1.00025MHz THIRD-ORDER IMD: –87.67dB 997 999 1001 1003 FREQUENCY (kHz) NORMAL MODE LOW POWER MODE MCLK FREQUENCY (MHz) –60dB –0.5dB 0 64 128 192 DECIMATION RATE AD7760 1005 40 –6dB 256 ...
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... AD7760 4500 4000 3500 3000 2500 2000 1500 1000 500 0 8385222 8385238 8385254 24-BIT CODE Figure 29. Normal Mode, 24-Bit Histogram, 256× Decimation 600 500 400 300 200 100 0 8385016 8385116 8385216 8385316 24-BIT CODE Figure 30. Normal Mode, 24-Bit Histogram, 8× Decimation 0.0010 +85° ...
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... Figure 38. Decimate × 32 Figure 39. Decimate × 256 2 Rev Page AD7760 ICLK FREQUENCY (MHz) vs. ICLK Frequency ( ICLK FREQUENCY (MHz) vs ...
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... The AD7760 employs three FIR filters in series. By using different combinations of decimation ratios, filter selection, and bypassing, data can be obtained from the AD7760 at a large range of data rates. Multibit data from the modulator can be obtained at the ICLK rate (see Modulator Data Output Mode section) ...
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... FREQUENCY (MHz) Figure 41. FFT of Data Output by the AD7760 in Modulator Output Mode MODULATOR DATA OUTPUT SCALING In modulator output mode, data is output in a 16-bit twos complement format on Pins D [15:0]; however, this data is scaled to 15 bits. The transfer function in Figure 42 shows the scaling involved for the 16 data bits output from Modulator Pins D[15:0] vs ...
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... DRDY CS, RD/ D[0:15] Figure 43. AD7760 Modulator Output Mode ( CDIV = 1) and ( CDIV = even) RESET MCLK SYNC Figure 44. AD7760 Relative Timing Between RESET and SYNC in Modulator Output Mode CDIV = 0 output mode when operating with CDIV = 1 (that is, ICLK = MCLK) ...
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... INVALID DATA MOD DATA Figure 45. AD7760 Modulator Output Mode ( CDIV = odd) 5. Write to Control Register 2 to power up the ADC and the differential amplifier as required. The correct clock divider ( CDIV ) ratio should be programmed at this time. Write to Control Register 1 to set the bypass filter bits, BYP F1 6 ...
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... AD7760 AD7760 INTERFACE READING DATA When the AD7760 is outputting data MHz output data rate or less, the interface operates in a conventional mode, as shown in Figure 2, using a 16-bit bidirectional parallel interface. This interface is controlled by the RD /WR and CS pins. The 24-bit conversion data is output in twos complement format. When a new conversion result is available, an active low pulse is output on the DRDY pin ...
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... Downloading a User-Defined Filter section. The AD7760 Registers section contains the register addresses and details. Figure 3 shows a write operation to the AD7760. The RD /WR line is held high while the CS line is brought low for a minimum of four ICLK periods. The register address is latched during this period ...
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... INL and THD performance to 16 MHz. BUFFERING THE MCLK SIGNAL The MCLK signal for the AD7760 must be buffered before being input to the MCLK pin on the AD7760 device. This can be done simply by routing the MCLK signal to both inputs of an AND gate (see Figure 47). ...
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... Figure 48. Maximum Slew Rate of Sine Wave with Amplitude p-p 1.0 0.5 0 –0.5 –1.0 Figure 49. Maximum Slew Rate of Sine Wave (with the Same Frequency as in Figure 48) with Amplitude p-p Rev Page AD7760 ...
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... AD7760 24-BIT OUTPUT 5 Figure 51. Transfer Function for the AD7760 Filtered Output Where V +3.685V +2.048V A +0.410V +3.685V B +2.048V +0.410V OUTPUTS OF THE AD7760 DIFFERENTIAL AMPLIFIER Figure 52. Differential Amplifier Signal Conditioning Rev Page that is, 0.8 × 4.096 V ≈ 3.275 V p-p REF 4) ...
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... To obtain maximum performance from the AD7760 advisable to drive the ADC with differential signals. Figure 53 shows how a bipolar, single-ended signal biased around ground can drive the AD7760 with the use of an external op amp, such as the AD8021 AD8021 ...
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... AD7760 DECOUPLING AND LAYOUT RECOMMENDATIONS Due to the high performance nature of the AD7760, correct decoupling and layout techniques are required to obtain the performance as stated within this data sheet. Figure 55 shows a simplified connection diagram for the AD7760 A– A– OUT ...
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... R17 10Ω EXPOSED PADDLE PIN 10 + The AD7760 64-lead TQFP employs × exposed C46 10nF paddle (see Figure 59). The paddle reduces the thermal resistance of the package by providing a path for heat energy to flow between the package and the PCB and, in turn, increases the heat transfer efficiency from the AD7760 package ...
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... AD7760 PROGRAMMABLE FIR FILTER As previously mentioned, the third FIR filter on the AD7760 is user programmable. The default coefficients that are loaded upon reset are given in Table 10, and the frequency responses are shown in Figure 57. The frequencies quoted in Figure 57 scale directly with the output data rate. ...
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... The same checksum is generated internally in the AD7760 and compared with the downloaded checksum. The DL_OK bit in the status register is set if these two checksums agree. ...
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... Table 14 lists the 16-bit words the user would write to the AD7760 to set up the ADC and download this filter, assuming an output data rate of 1.25 MHz has been selected. Table 14. Sequence of Write Instructions to Set Up Device and Download the Filter Example Word Word 2 ...
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... PD Power Down. Setting this bit powers down the AD7760, reducing the power consumption to 6.35 mW. 2 LPWR Low Power. If this bit is set, the AD7760 is operating in a low power mode. The power consumption is reduced for reduction in noise performance Write 1 to this bit. ...
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... OVR If the current analog input exceeds the current overrange threshold, this bit is set. 7 DL_OK When downloading a user filter to the AD7760, a checksum is generated. This checksum is compared to the one downloaded following the coefficients. If these checksums agree, this bit is set. 6 FILTOK When a user-defined filter is in use, a checksum is generated when the filter coefficients pass through the filter. This generated checksum is compared to the one downloaded ...
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... Dimensions shown in millimeters Package Description 64-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 64-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Evaluation Board Rev Page 10.20 10.00 SQ EXPOSED 9.80 BSC SQ PAD BOTTOM VIEW (PINS UP 0.50 0.38 BSC 0.32 LEAD PITCH 0.22 Package Option SV-64-2 SV-64-2 AD7760 6.00 ...
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... AD7760 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04975-0-8/06(A) Rev Page ...