AD7760 Analog Devices, AD7760 Datasheet - Page 28

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AD7760

Manufacturer Part Number
AD7760
Description
2.5 MSPS, 24-Bit, 100 dB Sigma-Delta ADC with On-Chip Buffer
Manufacturer
Analog Devices
Datasheet

Specifications of AD7760

Resolution (bits)
24bit
# Chan
1
Sample Rate
40MSPS
Interface
Par
Analog Input Type
Diff-Uni
Ain Range
4 V p-p,6.5 V p-p
Adc Architecture
Sigma-Delta
Pkg Type
QFP

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AD7760
DECOUPLING AND LAYOUT RECOMMENDATIONS
Due to the high performance nature of the AD7760, correct decoupling and layout techniques are required to obtain the performance as
stated within this data sheet. Figure 55 shows a simplified connection diagram for the AD7760.
AV
(RHS)
PIN 4
DD
2
100nF
C48
L1
(VBIAS)
PIN 15
100nF
100nF
C7
C50
L3
33pF
PIN 14
C64
(LHS)
100nF
C62
L2
V
V
OUT
OUT
V
V
V
160kΩ
REFX
IN
IN
V
V
IN
IN
A+
A–
A–
A+
R19
+
L9
PIN 27
19
20
21
22
30
25
26
10
17
35
42
43
53
62
64
(VBUF)
8
9
1
AV
PIN 12
V
V
V
V
DECAPA
DECAPB
V
V
V
REFGND
R
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DD
IN
IN
OUT
OUT
IN
IN
REF+
BIAS
4
A+
A–
+
10nF
A–
A+
R38
10Ω
C59
Figure 55. Simplified Connection Diagram
L4
(VMOD1)
AV
Rev. A | Page 28 of 36
PIN 5
DD
1
100nF
C52
L5
AD7760BSV
(VMOD2)
PIN 33
100nF
C53
L11
(VDIF1)
AV
PIN 24
DD
3
100nF
C54
L6
MCLKGND
U2
RD/WR
RESET
(VDRV1)
MCLK
SYNC
DRDY
DB10
DB11
DB12
DB13
DB14
DB15
V
PIN 44
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DRIVE
CS
100nF
61
60
59
58
57
56
55
54
52
51
50
49
48
47
46
45
40
39
37
36
38
3
2
C56
L7
DB [0:15]
(VDRV2)
PIN 63
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
100nF
CS
RD/WR
RESET
SYNC
DRDY
MCLK
C57
L12
(DV
PIN 41
DV
DD
DD
100nF
)
C58
L8

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