AD7760 Analog Devices, AD7760 Datasheet - Page 24

• Manufacturer Part Number: AD7760
• Description: 2.5 MSPS, 24-Bit, 100 dB Sigma-Delta ADC with On-Chip Buffer
• Manufacturer: Analog Devices

Specifications of AD7760

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 40MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 4 V p-p,6.5 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP

AD7760
CLOCKING THE AD7760
The AD7760 requires an external low jitter clock source. This
signal is applied to the MCLK pin, and the MCLKGND pin is
used to sense the ground from the clock source. An internal
clock signal (ICLK) is derived from the MCLK input signal. The
ICLK controls all internal operations of the AD7760. The
maximum ICLK frequency is 20 MHz, but due to an internal
clock divider, a range of MCLK frequencies can be used. There
are two ways to generate the ICLK:
These options are selected from the control register (see the
AD7760 Registers section for more details). On power-up, the
default is ICLK = MCLK/2 to ensure that the part can handle
the maximum MCLK frequency of 40 MHz. For output data
rates equal to those used in audio systems, a 12.288 MHz ICLK
frequency can be used. As shown in Table 6, output data rates of
192 kHz, 96 kHz, and 48 kHz are achievable with this ICLK
frequency. As mentioned previously, this ICLK frequency can
be derived from different MCLK frequencies.
It is recommended that the MCLK signal applied to the
AD7760 has a 50-50 mark-space ratio. When operating in clock
divide-by-1 mode (that is, CDIV = 1), using higher mark-space
ratios reduces the maximum MCLK frequency that can be
applied to the AD7760 yielding maximum performance. For
example, using a mark-space ratio of 60-40 (with CDIV = 1)
reduces the maximum MCLK frequency that will yield the
maximum INL and THD performance to 16 MHz.
BUFFERING THE MCLK SIGNAL
The MCLK signal for the AD7760 must be buffered before
being input to the MCLK pin on the AD7760 device. This can
be done simply by routing the MCLK signal to both inputs of an
AND gate (see Figure 47).
The recommended buffer is the NC7SZ08M5, which is a two-
input AND gate from Fairchild Semiconductor. Using the buffer
with a supply voltage of 5 V is advised to achieve optimum
performance from the AD7760.
Figure 47. Buffering the MCLK Signal Using the NC7SZ08M5 AND Gate
ICLK = MCLK ( CDIV = 1)
ICLK = MCLK/2 ( CDIV = 0)
SOURCE
MCLK
(AND GATE)
NC7SZ08M5
3
MCLK
AD7760
Rev. A | Page 24 of 36
MCLK JITTER REQUIREMENTS
The MCLK jitter requirements depend on a number of factors
and are given by
where:
OSR = oversampling ratio = f
f
SNR(dB) = target SNR.
Example 1
This example can be taken from Table 6, where:
ODR = 2.5 MHz.
f
f
SNR = 108 dB.
This is the maximum allowable clock jitter for a full-scale,
1 MHz input tone with the given ICLK and output data rate.
Example 2
Take a second example from Table 6, where:
ODR = 48 kHz.
f
f
SNR = 120 dB.
The input amplitude also has an effect on these jitter figures.
For example, if the input level was 3 dB below full-scale, the
allowable jitter would be increased by a factor of √2, increasing
the first example to 2.53 ps rms. This happens when the
maximum slew rate is decreased by a reduction in amplitude.
Figure 48 and Figure 49 illustrate this point, showing the
maximum slew rate of a sine wave of the same frequency but
with different amplitudes.
IN
ICLK
IN
ICLK
IN
= maximum input frequency.
(max) = 1 MHz.
(max) = 19.2 kHz.
= 20 MHz.
= 12.288 MHz.
t
t
t
j
j
j
(
(
(
rms
rms
rms
)
)
)
=
=
=
2
2
2
×
×
×
π
π
π
×
×
×
19
10
f
IN
8
2 .
6
256
×
×
OSR
×
10
10
10
5
SNR
3
4 .
ICLK
×
=
10
20
/ODR.
. 1
(
6
dB
79
=
)
133
ps
ps