AD9228 Analog Devices, AD9228 Datasheet - Page 7

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AD9228

Manufacturer Part Number
AD9228
Description
Quad, 12-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD9228

Resolution (bits)
12bit
# Chan
4
Sample Rate
65MSPS
Interface
LVDS,Ser
Analog Input Type
Diff-Uni,SE-Uni
Ain Range
2 V p-p
Adc Architecture
Pipelined
Pkg Type
CSP

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Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
Parameter
CLOCK
OUTPUT PARAMETERS
APERTURE
1
2
3
4
See the
Measured on standard FR-4 material.
Can be adjusted via the SPI.
t
SAMPLE
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (t
Clock Pulse Width Low (t
Propagation Delay (t
Rise Time (t
Fall Time (t
FCO Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Delay (t
DCO to FCO Delay (t
Data to Data Skew
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)
Pipeline Latency
Aperture Delay (t
Aperture Uncertainty (Jitter)
Out-of-Range Recovery Time
(t
/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
3
DATA-MAX
AN-835 Application
1
, 2
F
R
) (20% to 80%)
− t
) (20% to 80%)
DATA-MIN
A
)
PD
DATA
3
FRAME
)
)
)
EL
4
EH
)
)
Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
4
)
FCO
CPD
)
)
4
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
25°C
25°C
25°C
Min
40
2.0
2.0
(t
(t
SAMPLE
SAMPLE
/24) − 300
/24) − 300
AD9228-40
Typ
12.5
12.5
2.7
300
300
2.7
t
(t
(t
(t
±50
600
375
8
500
<1
1
FCO
SAMPLE
SAMPLE
SAMPLE
+
Rev. E | Page 7 of 56
/24)
/24)
/24)
Max
10
3.5
3.5
(t
(t
±150
SAMPLE
SAMPLE
/24) + 300
/24) + 300
Min
65
2.0
2.0
(t
(t
SAMPLE
SAMPLE
/24) − 300
/24) − 300
AD9228-65
Typ
7.7
7.7
2.7
300
300
2.7
t
(t
(t
(t
±50
600
375
8
500
<1
2
FCO
SAMPLE
SAMPLE
SAMPLE
+
/24)
/24)
/24)
Max
10
(t
(t
±150
3.5
3.5
SAMPLE
SAMPLE
/24) + 300
/24) + 300
AD9228
Unit
MSPS
MSPS
ns
ns
ns
ps
ps
ns
ns
ps
ps
ps
ns
μs
CLK
cycles
ps
ps rms
CLK
cycles

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