AD9228 Analog Devices, AD9228 Datasheet - Page 22

• Manufacturer Part Number: AD9228
• Description: Quad, 12-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9228

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 65MSPS
• Interface: LVDS,Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9228
For best dynamic performance, the source impedances driving
VIN + x and VIN − x should be matched such that common-
mode settling errors are symmetrical. These errors are reduced
by the common-mode rejection of the ADC. An internal
reference buffer creates the positive and negative reference
voltages, REFT and REFB, respectively, that define the span of
the ADC core. The output common-mode of the reference buffer
is set to midsupply, and the REFT and REFB voltages and span
are defined as
It can be seen from these equations that the REFT and REFB
voltages are symmetrical about the midsupply voltage and, by
definition, the input span is twice the value of the VREF voltage.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD9228, the largest input span available is 2 V p-p.
Differential Input Configurations
There are several ways to drive the AD9228 either actively or
passively; however, optimum performance is achieved by driving
the analog input differentially. For example, using the
differential driver to drive the AD9228 provides excellent perfor-
mance and a flexible interface to the ADC (see Figure 51) for
baseband applications. This configuration is commonly used
for medical ultrasound systems.
For applications where SNR is a key parameter, differential
transformer coupling is the recommended input configuration
(see Figure 48 and Figure 49), because the noise performance of
most amplifiers is not adequate to achieve the true performance
of the AD9228.
Regardless of the configuration, the value of the shunt capacitor,
C, is dependent on the input frequency and may need to be
reduced or removed.
REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
1V p-p
0.1μF
120nH
Figure 51. Differential Input Configuration Using the
0.1μF
22pF
18nF
INH
LMD
274Ω
LNA
LOP
LON
AD8332
AD8332
0.1μF
0.1μF
Rev. E | Page 22 of 56
VIP
VIN
VGA
VOH
VOL
AD8332
2V p-p
Single-Ended Input Configuration
A single-ended input may provide adequate performance in cost-
sensitive applications. In this configuration, SFDR and distortion
performance degrade due to the large input common-mode swing.
If the application requires a single-ended input configuration,
ensure that the source impedances on each input are well matched
in order to achieve the best possible performance. A full-scale
input of 2 V p-p can be applied to the ADC’s VIN + x pin while
the VIN − x pin is terminated. Figure 50 details a typical single-
ended input configuration.
2V p-p
187Ω
187Ω
2V p-p
with Two-Pole, 16 MHz Low-Pass Filter
65Ω
Figure 48. Differential Transformer-Coupled Configuration
16nH
Figure 49. Differential Transformer-Coupled Configuration
680nH
680nH
68pF
1kΩ
1kΩ
LPF
AVDD
49.9Ω
0.1μF
49.9Ω
Figure 50. Single-Ended Input Configuration
1kΩ
1kΩ
+
AVDD
0.1µF
33Ω
33Ω
1:1 Z RATIO
ADT1-1WT
AVDD
AVDD
1:1 Z RATIO
0.1µF
ADT1-1WT
for Baseband Applications
10kΩ
10kΩ
0.1μF
10kΩ
10kΩ
1kΩ 25Ω
1kΩ
for IF Applications
AVDD
0.1μF
1kΩ
499Ω
16nH
AVDD
16nH
1kΩ
*C
*C
R
R
*C
*C
DIFF
DIFF IS OPTIONAL
DIFF
DIFF IS OPTIONAL
R
2.2pF
33Ω
33Ω
R
C
C
C
C
VIN + x
VIN – x
AD9228
ADC
1kΩ
VIN + x
VIN – x
VIN + x
VIN – x
Data Sheet
AD9228
AD9228
ADC
ADC
VIN + x
VIN – x
AGND
AD9228
ADC