AD9228 Analog Devices, AD9228 Datasheet - Page 28

• Manufacturer Part Number: AD9228
• Description: Quad, 12-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9228

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 65MSPS
• Interface: LVDS,Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9228
When the SPI is used, the DCO phase can be adjusted in 60°
increments relative to the data edge. This enables the user to
refine system timing margins if required. The default DCO+
and DCO− timing, as shown in Figure 2, is 90° relative to the
output data edge.
An 8-, 10-, or 14-bit serial stream can also be initiated from the
SPI. This allows the user to implement and test compatibility to
lower and higher resolution systems. When changing the
resolution to an 8- or 10-bit serial stream, the data stream is
shortened. See Figure 3 for the 10-bit example. However, when
using the 14-bit option, the data stream stuffs two 0s at the end
of the 14-bit serial data.
When the SPI is used, all of the data outputs can also be
inverted from their nominal state. This is not to be confused
with inverting the serial stream to an LSB-first mode. In default
mode, as shown in Figure 2, the MSB is first in the data output
serial stream. However, this can be inverted so that the LSB is
first in the data output serial stream (see Figure 4).
There are 12 digital output test pattern options available that
can be initiated through the SPI. This is a useful feature when
validating receiver capture and timing. Refer to Table 9 for the
output bit sequencing options available. Some test patterns have
two serial sequential words and can be alternated in various
ways, depending on the test pattern chosen. Note that some
patterns do not adhere to the data format select option. In
addition, custom user-defined test patterns can be assigned in
the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode
options except PN sequence short and PN sequence long can
support 8- to 14-bit word lengths in order to verify data capture
to the receiver.
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 2
description of the PN sequence and how it is generated can be
found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The
only difference is that the starting value must be a specific value
instead of all 1s (see Table 10 for the initial values).
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 2
description of the PN sequence and how it is generated can be
found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The
only differences are that the starting value must be a specific
value instead of all 1s (see Table 10 for the initial values) and the
AD9228 inverts the bit stream with relation to the ITU standard.
9
23
− 1 or 511 bits. A
− 1 or 8,388,607 bits. A
Rev. E | Page 28 of 56
Table 10. PN Sequence
Sequence
PN Sequence Short
PN Sequence Long
Consult the Memory Map section for information on how to
change these additional digital output timing features through
the SPI.
SDIO/ODM Pin
The SDIO/ODM pin is for use in applications that do not require
SPI mode operation. This pin can enable a low power, reduced
signal option (similar to the IEEE 1596.3 reduced range link
output standard) if it and the CSB pin are tied to AVDD during
device power-up. This option should only be used when the
digital output trace lengths are less than 2 inches from the LVDS
receiver. When this option is used, the FCO, DCO, and outputs
function normally, but the LVDS signal swing of all channels is
reduced from 350 mV p-p to 200 mV p-p, allowing the user to
further reduce the power on the DRVDD supply.
For applications where this pin is not used, it should be tied low.
In this case, the device pin can be left open, and the 30 kΩ internal
pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant.
If applications require this pin to be driven from a 3.3 V logic level,
insert a 1 kΩ resistor in series with this pin to limit the current.
Table 11. Output Driver Mode Pin Settings
Selected ODM
Normal
ODM
Operation
ODM Voltage
10 kΩ to AGND
AVDD
Initial
Value
0x0df
0x29b80a
Resulting
Output Standard
ANSI-644
(default)
Low power,
reduced
signal option
First Three Output Samples
(MSB First)
0xdf9, 0x353, 0x301
0x591, 0xfd7, 0x0a3
Data Sheet
Resulting
FCO and DCO
ANSI-644
(default)
Low power,
reduced
signal option