AD9228 Analog Devices, AD9228 Datasheet - Page 24

• Manufacturer Part Number: AD9228
• Description: Quad, 12-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9228

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 65MSPS
• Interface: LVDS,Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9228
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (f
due only to aperture jitter (t
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 57).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9228.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators are
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or another method), it
should be retimed by the original clock during the last step.
Refer to the
Application Note
performance as it relates to ADCs.
SNR Degradation = 20 × log 10(1/2 × π × f
130
120
110
100
90
80
70
60
50
40
30
1
10 BITS
Figure 57. Ideal SNR vs. Input Frequency and Jitter
RMS CLOCK JITTER REQUIREMENT
AN-501 Application Note
for more in-depth information about jitter
ANALOG INPUT FREQUENCY (MHz)
10
J
) can be calculated by
0.125 ps
0.25 ps
0.5 ps
1.0 ps
2.0 ps
and to the
100
A
× t
AN-756
J
)
14 BITS
12 BITS
16 BITS
1000
Rev. E | Page 24 of 56
A
)
Power Dissipation and Power-Down Mode
As shown in Figure 58 and Figure 59, the power dissipated by
the AD9228 is proportional to its sample rate. The digital power
dissipation does not vary significantly because it is determined
primarily by the DRVDD supply and bias current of the LVDS
output drivers.
Figure 58. Supply Current vs. f
Figure 59. Supply Current vs. f
250
200
150
100
180
160
140
120
100
50
80
60
40
20
0
0
10
10
AVDD CURRENT
AVDD CURRENT
15
20
DRVDD CURRENT
DRVDD CURRENT
20
30
ENCODE (MSPS)
ENCODE (MSPS)
SAMPLE
SAMPLE
25
for f
for f
40
IN
IN
TOTAL POWER
TOTAL POWER
= 10.3 MHz, f
= 10.3 MHz, f
30
50
Data Sheet
35
SAMPLE
SAMPLE
60
= 40 MSPS
= 65 MSPS
40
480
460
440
420
400
380
360
340
320
300
360
340
320
300
280
260
240
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200
180