AD9228 Analog Devices, AD9228 Datasheet - Page 34

• Manufacturer Part Number: AD9228
• Description: Quad, 12-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9228

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 65MSPS
• Interface: LVDS,Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9228
Table 16. Memory Map Register
Addr.
(Hex)
Chip Configuration Registers
00
01
02
Device Index and Transfer Registers
05
FF
ADC Functions
08
09
0D
Register Name
chip_port_config
chip_grade
device_update
test_io
chip_id
device_index_A
modes
clock
(MSB)
Bit 7
0
X
X
X
X
X
User test mode
00 = off (default)
01 = on, single alternate
10 = on, single once
11 = on, alternate once
Bit 6
LSB first
1 = on
0 = off
(default)
Child ID [6:4]
(identify device variants of Chip ID)
000 = 65 MSPS
001 = 40 MSPS
X
X
X
X
Bit 5
Soft
reset
1 = on
0 = off
(default)
Clock
Channel
DCO
1 = on
0 = off
(default)
X
X
X
Reset PN
long gen
1 = on
0 = off
(default)
(AD9228 = 0x02), (default)
8-bit Chip ID Bits [7:0]
Bit 4
1
Clock
Channel
FCO
1 = on
0 = off
(default)
X
X
X
Reset
PN short
gen
1 = on
0 = off
(default)
Rev. E | Page 34 of 56
1
X
Data
Channel
D
1 = on
(default)
0 = off
X
X
X
Output test mode—see Table 9 in the
Digital Outputs and Timing section
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checkerboard output
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
(format determined by output_mode)
Bit 3
Bit 2
Soft
reset
1 = on
0 = off
(default)
X
Data
Channel
C
1 = on
(default)
0 = off
X
Internal power-down mode
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset
X
Bit 1
LSB first
1 = on
0 = off
(default)
X
Data
Channel
B
1 = on
(default)
0 = off
X
X
(LSB)
Bit 0
0
X
Data
Channel
A
1 = on
(default)
0 = off
SW
transfer
1 = on
0 = off
(default)
Duty
cycle
stabilizer
1 = on
(default)
0 = off
Default
Value
(Hex)
0x18
0x02
Read
only
0x0F
0x00
0x00
0x01
0x00
Data Sheet
Default Notes/
Comments
The nibbles
should be
mirrored so that
LSB- or MSB-first
mode is set cor-
rectly regardless
of shift mode.
Default is unique
chip ID, different
for each device.
This is a read-
only register.
Child ID used to
differentiate
graded devices.
Bits are set to
determine which
on-chip device
receives the next
write command.
Synchronously
transfers data
from the master
shift register to
the slave.
Determines
various generic
modes of chip
operation.
Turns the
internal duty
cycle stabilizer
on and off.
When this reg-
ister is set, the
test data is placed
on the output
pins in place of
normal data.