AD6659 Analog Devices, AD6659 Datasheet - Page 35

• Manufacturer Part Number: AD6659
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6659

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
Sync Control (Register 0x100)
Bits[7:3]—Open
Bit 2—Clock Divider Next Sync Only
If the master sync enable bit (Address 0x100, Bit 0) and the clock
divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2
allows the clock divider to sync to the first sync pulse that it
receives and to ignore the rest. The clock divider sync enable
bit (Address 0x100, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal
is enabled when Bit 1 and Bit 0 are high and the device is operating
in continuous sync mode as long as Bit 2 of the sync control
register is low.
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions.
USR2 (Register 0x101)
Bit 7—Enable OEB Pin 47 (Local)
Normally set high, this bit allows Pin 47 to function as the
output enable. If it is set low, it disables Pin 47.
Bits[6:4]—Open
Bit 3—Enable GCLK Detect
Normally set high, this bit enables a circuit that detects encode
rates below approximately 5 MSPS. When a low encode rate is
detected, an internal oscillator, GCLK, is enabled ensuring the
proper operation of several circuits. If set low, the detector is
disabled.
Bit 2—Run GCLK
This bit enables the GCLK oscillator. For some applications
with encode rates below 10 MSPS, it may be preferable to set
this bit high to supersede the GCLK detector (Bit 3).
Bit 1—Open
Bit 0—Disable SDIO Pull-Down
This bit can be set high to disable the internal 30 kΩ pull-down
on the SDIO pin, which can be used to limit the loading when
many devices are connected to the SPI bus.
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QEC Control 0 (Register 0x110)
Bits[7:6]—Open
Bits[5:3]—Freeze DC/Freeze Phase/Freeze Gain
These bits can be used to freeze the corresponding dc, phase,
and gain offset corrections of the quadrature error correction
(QEC) independently. When asserted high, QEC is applied
using frozen values, and the estimation of the quadrature errors
is halted.
Bits[2:0]—DC Enable/Phase Enable/Gain Enable
These bits allow the corresponding dc, phase, and gain offset
corrections to be enabled independently.
QEC Control 1 (Register 0x111)
Bits[7:3]—Open
Bit 2—Force DC
When set high, this bit forces the initial static correction values
from Register 0x11A and Register 0x11B for the I data and
Register 0x11C and Register 0x11D for the Q data.
Bit 1—Force Phase
When set high, this bit forces the initial static correction values
from Register 0x118 and Register 0x119.
Bit 0—Force Gain
When set high, this bit forces the initial static correction values
from Register 0x116 and Register 0x117.
QEC Gain Bandwidth Control (Register 0x112)
Bits[7:5]—Open
Bits[4:0]—Kexp_Gain[4:0]
These bits adjust the time constants of the gain control feedback
loop for quadrature error correction.
QEC Phase Bandwidth Control (Register 0x113)
Bits[7:5]—Open
Bits[4:0]—Kexp_Phase[4:0]
These bits adjust the time constants of the phase control
feedback loop for quadrature error correction.
QEC DC Bandwidth Control (Register 0x114)
Bits[7:5]—Open
Bits[4:0]—Kexp_DC[4:0]
These bits adjust the time constants of the dc control feedback
loop for quadrature error correction.
AD6659