AD6659 Analog Devices, AD6659 Datasheet - Page 22

• Manufacturer Part Number: AD6659
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6659

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD6659
which is determined by the sample rate and the characteristics
of the analog input signal.
Reducing the capacitive load presented to the output drivers
can minimize digital power consumption. The data in Figure 44
was taken using the same operating conditions as those used for the
Typical Performance Characteristics, with a 5 pF load on each
output driver.
The AD6659 is placed in power-down mode either by the SPI
port or by asserting the PDWN pin high. In this state, the ADC
typically dissipates 1.0 mW. During power-down, the output
drivers are placed in a high impedance state. By asserting the
PDWN pin low returns the AD6659 to its normal operating
mode. Note that PDWN is referenced to the digital output driver
supply (DRVDD) and should not exceed that supply voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and must then be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map section
for more details.
DIGITAL OUTPUTS
The AD6659 output drivers can be configured to interface with
1.8 V to 3.3 V CMOS logic families. Output data can also be
multiplexed onto a single output bus to reduce the total number
of traces required.
210
190
170
150
130
110
90
70
10
Figure 44. Analog Core Power vs. Clock Rate
20
30
CLOCK RATE (MSPS)
40
50
60
70
80
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The CMOS output drivers are sized to provide sufficient output
current to drive a wide variety of logic families. However, large
drive currents tend to cause current glitches on the supplies and
may affect converter performance.
Applications that require the ADC to drive large capacitive
loads or large fanouts may require external buffers or latches.
The output data format can be selected to be either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 11). Output codings for the
respective data formats are shown in Table 12.
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.
Table 11. SCLK/DFS Mode Selection (External Pin Mode)
Voltage at Pin
AGND
DRVDD
Digital Output Enable Function (OEB)
The AD6659 has a flexible three-state ability for the digital output
pins. The three-state mode is enabled using the OEB pin or
through the SPI interface. If the OEB pin is low, the output data
drivers and DCOs are enabled. If the OEB pin is high, the output
data drivers and DCOs are placed in a high impedance state.
This OEB function is not intended for rapid access to the data
bus. Note that OEB is referenced to the digital output driver
supply (DRVDD) and should not exceed that supply voltage.
When using the SPI interface, the data outputs and DCO of
each channel can be independently three-stated by using the
output disable (OEB) bit (Bit 4) in Register 0x14.
TIMING
The AD6659 provides latched data with a pipeline delay of nine
clock cycles. Data outputs are available one propagation delay
(t
Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD6659. These transients
can degrade converter dynamic performance.
The lowest typical conversion rate of the AD6659 is 3 MSPS. At
clock rates below 3 MSPS, dynamic performance can degrade.
Data Clock Output (DCOx)
The AD6659 provides two data clock output (DCOx) signals
intended for capturing the data in an external register. The
CMOS data outputs are valid on the rising edge of DCOx, unless
the DCOx clock polarity was changed via the SPI. See Figure 2 and
Figure 3 for graphical timing descriptions.
PD
) after the rising edge of the clock signal.
SCLK/DFS
Offset binary (default)
Twos complement
SDIO/DCS
DCS disabled (default)
DCS enabled