AD6659 Analog Devices, AD6659 Datasheet - Page 29

• Manufacturer Part Number: AD6659
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6659

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

SERIAL PORT INTERFACE (SPI)
The AD6659 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space provided inside the ADC. The SPI gives the user added
flexibility and customization, depending on the application.
Addresses are accessed via the serial port and can be written to
or read from the port. Memory is organized into bytes that can
be further divided into fields, which are documented in the
Memory Map section. For detailed operational information, see
the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: SCLK, SDIO, and CSB
(see Table 14). SCLK (a serial clock) is used to synchronize the
read and write data presented from and to the ADC. SDIO (serial
data input/output) is a dual-purpose pin that allows data to be
sent to and read from the internal ADC memory map registers.
CSB (chip select bar) is an active low control that enables or
disables the read and write cycles.
Table 14. Serial Port Interface Pins
Pin
SCLK
SDIO
CSB
CSB
SCLK
SDIO
Serial Clock. The serial shift clock input, which is used
Description
to synchronize serial interface reads and writes.
Serial Data Input/Output. A dual-purpose pin that typically
serves as an input or an output, depending on the
instruction being sent and the relative position in the
timing frame.
Chip Select Bar. An active low control that gates the
read and write cycles.
DON’T
DON’T
CARE
CARE
t
S
R/W
t
DS
W1
W0
t
DH
A12
t
HIGH
A11
Figure 50. Serial Port Interface Timing Diagram
t
LOW
A10
A9
Rev. | Page 29 of 40
t
CLK
A8
A7
The falling edge of CSB, in conjunction with the rising edge of
SCLK, determines the start of the framing. An example of the
serial timing and its definitions can be found in Figure 50 and
Table 5.
Other modes involving CSB are available. CSB can be held low
indefinitely, which permanently enables the device; this is called
streaming. CSB can stall high between bytes to allow for additional
external timing. When CSB is tied high, SPI functions are placed
in high impedance mode. This mode turns on any SPI pin
secondary functions.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W1 and W0 bits, as shown in Figure 50.
All data is composed of 8-bit words. The first bit of the first byte
in a multibyte serial data transfer frame indicates whether a read
command or a write command is issued. This allows the serial
data input/output (SDIO) pin to change direction from an input
to an output at the appropriate point in the serial frame.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.
Data can be sent in MSB-first mode or LSB-first mode. MSB-
first mode is the default on power-up and can be changed via
the SPI port configuration register. For more information about
this and other features, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
D5
D4
D3
D2
D1
D0
t
H
DON’T
CARE
DON’T
CARE
AD6659