SAM3N0A Atmel Corporation, SAM3N0A Datasheet - Page 637
SAM3N0A
Manufacturer Part Number
SAM3N0A
Description
Manufacturer
Atmel Corporation
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32.6.3.4
11011A–ATARM–04-Oct-10
Interrupts
Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end
of the corresponding channel period. The interrupt remains active until a read operation in the
PWM_ISR register occurs.
A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A chan-
nel interrupt is disabled by setting the corresponding bit in the PWM_IDR register.
SAM3N
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