SAM3N0A Atmel Corporation, SAM3N0A Datasheet - Page 460
SAM3N0A
Manufacturer Part Number
SAM3N0A
Description
Manufacturer
Atmel Corporation
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• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
The delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the
character transfers.
Otherwise, the following equation determines the delay:
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
Delay Between Consecutive Transfers
=
32
------------------------------------ -
×
MCK
DLYBCT
SAM3N
SAM3N
460
460
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