SAM3N0A Atmel Corporation, SAM3N0A Datasheet - Page 421

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SAM3N0A

Manufacturer Part Number
SAM3N0A
Description
Manufacturer
Atmel Corporation
Datasheets
26.7.37
Name:
Addresses:
Access:
• P0-P31: Additional Interrupt Modes Disable.
0 = No effect.
1 = The interrupt mode is set to the default interrupt mode (Both Edge detection).
26.7.38
Name:
Addresses:
Access:
• P0-P31: Peripheral CD Status.
0 = The interrupt source is a Both Edge detection event
1 = The interrupt source is described by the registers PIO_ELSR and PIO_FRLHSR
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
P31
P23
P15
P31
P23
P15
P7
P7
31
23
15
31
23
15
7
7
PIO Additional Interrupt Modes Disable Register
PIO Additional Interrupt Modes Mask Register
P30
P22
P14
P30
P22
P14
P6
P6
30
22
14
30
22
14
PIO_AIMDR
0x400E0EB4 (PIOA), 0x400E10B4 (PIOB), 0x400E12B4 (PIOC)
Write-only
6
PIO_AIMMR
0x400E0EB8 (PIOA), 0x400E10B8 (PIOB), 0x400E12B8 (PIOC)
Read-only
6
P29
P21
P13
P29
P21
P13
P5
P5
29
21
13
29
21
13
5
5
P28
P20
P12
P28
P20
P12
P4
P4
28
20
12
28
20
12
4
4
P27
P19
P11
P27
P19
P11
P3
P3
27
19
11
27
19
11
3
3
P26
P18
P10
P26
P18
P10
P2
P2
26
18
10
26
18
10
2
2
P25
P17
P25
P17
P9
P1
P9
P1
25
17
25
17
9
1
9
1
SAM3N
SAM3N
P24
P16
P24
P16
P8
P0
P8
P0
24
16
24
16
8
0
8
0
421
421

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