SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 204
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SAM9X25
Manufacturer Part Number
SAM9X25
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X25
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
2
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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- SAM9X25 PDF datasheet #3
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- SAM9X25 PDF datasheet #5
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Signal Descriptions
A-16
Signal
IRDMAADR[17:0]
IRDMAEN
IRDMACS
IRIDLE
IRnRW
IRRD[31:0]
IRSEQ
IRSIZE[3:0]
Copyright © 2001-2003 ARM Limited. All rights reserved.
Direction
Input
Input
Input
Output
Output
Input
Output
Input
Function
DMA access cycle.
If asserted, IRADDR is directly sourced from
IRDMAADDR, and IRCS is the result of logically
ORing IRDMACS with the chip select value for the
current TCM access.
Enables direct memory access to the ITCM memory
using the IRDMAADDR and IRDMACS inputs.
Direct memory access chip-select for ITCM.
Instruction TCM interface idle:
0 = TCM access
1 = no access will take place in the current cycle or
TCM disabled.
Not valid for DMA accesses.
Instruction TCM read not write:
0 = read
1 = write.
Indicates if the access is a read or write. Valid during
request cycles.
Instruction TCM read data.
Valid during non-waited data cycles.
Request sequential.
Valid during request cycles, asserted during wait
cycles.
Indicates that the address in the current cycle is
sequential to the address used during the previous
request cycle.
IRSEQ is not valid following ITCM DMA accesses.
Instruction TCM size.
Static configuration input that specifies the physical
size of TCM memories attached.
0000 = absent
0011 = 4KB
0100 = 8KB
…
1010 = 512KB
1011 = 1MB
Values 0001, 0010, and 1100 to 1111 are reserved.
Table A-7 TCM interface signals (continued)
ARM DDI0198D
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