SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 133
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SAM9X25
Manufacturer Part Number
SAM9X25
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X25
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
2
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 133 of 248
- Download datasheet (2Mb)
ARM DDI0198D
The address and chip-select inputs to the ROM are pipelined with respect to the
ARM926EJ-S TCM interface outputs. An address incrementer is used to generate
sequential addresses. The output of the incrementer is captured at the end of every cycle
where the ROM CS chip select is active. The address source for the ROM is switched
over to the registered version of IRADDR when a nonsequential access occurs.
Figure 5-17 on page 5-26 shows the timing of the ROM address, chip-select, and read
data relative to the ARM926EJ-S TCM interface signals. The address supplied to the
ROM can either be behind, in sync with, or ahead of IRADDR, depending on the type
of memory access and the presence of idle cycles.
Figure 5-16 TCM subsystem that uses wait states for nonsequential accesses
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM926EJ-S
IRADDR[17:0]
IRRD[31:0]
IRWAIT
IRSEQ
IRCS
EN
1
0
+1
Tightly-Coupled Memory Interface
CS
A
RD
ROM
5-25
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