SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 701

• Manufacturer Part Number: SAM9261
• Manufacturer: Atmel Corporation

Specifications of SAM9261

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 160
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

42.2.10.5
42.2.10.6
42.2.10.7
42.2.10.8
42.2.11
42.2.11.1
6062N–ATARM–3-Oct-11
Serial Synchronous Controller (SSC)
SPI: Baudrate set to 1
SPI: Software Reset
SPI: Software Reset Must be Written Twice
SPI: Bad Serial Clock Generation on 2nd Chip Select
SSC: Transmitter Limitations in Slave Mode
If a PDC transfer has to be performed in 8 bits, on a Chip select y (y different from 0), the field
BITS of the CSR0 must be configured in 8 bits in the same way as the field BITS of the CSRy
Register.
When Baudrate is set at 1 (i.e. when serial clock frequency equals the system clock frequency),
and when the fields BITS (number of bits to be transmitted) equals an ODD value (in this case
9,11,13 or 15), an additional pulse is generated on output SPCK. No problem occurs if BITS field
equals 8,10,12,14 or 16 and Baudrate = 1.
None.
If the Software reset command is performed at the same clock cycle as an event for TXRDY
occurs, there is no reset.
Perform another software reset.
If a software reset (SWRST in the SPI control register) is performed, the SPI may not work prop-
erly (the clock is enabled before the chip select).
The SPI Control Register field, SWRST needs to be written twice to be correctly set.
Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0.
This occurs using SPI with the following conditions:
Do not use a multiple Chip Select configuration where at least one SCRx register is configured
with SCBR = 1 and the others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
If TK is programmed as input and TF is programmed as output and requested to be set to
low/high during data emission, the Frame Synchro is generated one bit clock period after the
data start, one data bit is lost. This problem does not exist when generating periodic synchro.
• Master Mode
• CPOL = 1 and NCPHA = 0
• Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when
• Transmitting with the slowest chip select and then with the fastest one, then an additional
serial clock frequency equals the system clock frequency) and the other transfers set with
SCBR are not equal to 1
pulse is generated on output SPCK during the second transfer.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9261
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