SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 677
SAM9261
Manufacturer Part Number
SAM9261
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9261.pdf
(749 pages)
4.SAM9261.pdf
(44 pages)
5.SAM9261.pdf
(1274 pages)
6.SAM9261.pdf
(43 pages)
Specifications of SAM9261
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
160
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9261 PDF datasheet #5
- SAM9261 PDF datasheet #6
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39.7
Table 39-16. Power-On-Reset Characteristics
39.7.1
39.7.2
6062N–ATARM–3-Oct-11
Symbol
V
V
T
th+
th-
RES
Core Power Supply POR CHaracteristics
Power Sequence Requirements
Power-Up Sequence
Parameter
Threshold Voltage Rising
Threshold Voltage Falling
Reset Time
The AT91SAM9261 board design must comply with the power-up guidelines below to guarantee
reliable operation of the device. Any deviation from these sequences may prevent the device
from booting.
Figure 39-3.
VDDCORE and VDDBU are controlled by internal POR (Power-On-Reset) to guarantee that
these power sources reach their target values prior to the release of POR.
• VDDIOP must be ≥ to V
• VDDIOM must reach V
+ T1) after VDDCORE has reached
+T2) after VDDCORE has reached
– T
– T1 = 3 x T
– T2 = 16 x T
RES
VDDCOREtyp
Core Supply POR Output
is a POR characteristic
VDDIOtyp
VDD (V)
VDDCORE and VDDIO Constraints at Startup
SLCK
Vth+
Voh
Vih
SLCK
SLCK
Conditions
Minimum Slope of +2.0V/30ms
OH
IH
(refer to DC characteristics
(refer to DC characteristics table for more details) within (Tres +T1
V
V
th+
th+
.
<--- Tres --->
< T1 >
<------------ T2----------->
Min
Table 39-2
0.7
0.6
50
Typ
170
0.9
0.8
for more details) within (Tres
AT91SAM9261
VDDIO > Vih
VDDIO > Voh
VDDCORE
Max
1.08
300
1.0
VDDIO
t
Units
µs
V
V
677
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