SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 616

• Manufacturer Part Number: SAM9261
• Manufacturer: Atmel Corporation

Specifications of SAM9261

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 160
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

38.5.1.3
38.5.1.4
38.5.1.5
38.5.2
38.5.2.1
38.5.2.2
616
AT91SAM9261
LCD Controller Core
Channel-U
Channel-L
Control
Configuration Block
Datapath
BRSTLN field of the DMAFRMCFG register. For details on this register, see
figuration Register” on page
This block stores the base address and the number of words transferred for this channel (frame
in single scan mode and Upper Panel in dual scan mode) since the beginning of the frame. It
also generates the end of frame signal.
It has two pointers, the base address and the number of words to transfer. When the module
receives a new_frame signal, it reloads the number of words to transfer pointer with the size of
the frame/panel. When the module receives the new_frame signal, it also reloads the base
address with the base address programmed by the host.
The size of the frame/panel can be programmed in the FRMSIZE field of the DMAFRMCFG
Register. This size is calculated as follows:
where:
This block has the same functionality as Channel-U, but for the Lower Panel in dual scan mode
only.
This block receives the request signals from the LCDC core and generates the requests for the
channels.
The configuration block is a set of programmable registers that are used to configure the LCDC
core operation. These registers are written via the AHB slave interface. Only word access is
allowed.
The description of the configuration registers can be found in
Interface” on page
The datapath block contains five submodules: FIFO, Serializer, Palette, Dithering and Shifter.
The structure of the datapath is shown in
• Display_size =Horizontal_display_size x Vertical_display_size
• Bpp is the bits per pixel configuration
Frame_size
639.
=
645.
Display_size
-------------------------------------------------- -
32
Figure
×
Bpp
38-2.
“LCD Controller (LCDC) User
“DMA Frame Con-
6062N–ATARM–3-Oct-11