SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 40

• Manufacturer Part Number: SAM9261
• Manufacturer: Atmel Corporation

Specifications of SAM9261

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 160
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

11.2
Figure 11-1. ARM926EJ-S Internal Functional Block Diagram
11.3
11.3.1
11.3.2
40
Block Diagram
ARM9EJ-S Processor
AT91SAM9261
ARM9EJ-S Operating States
Switching State
Interface
ICE
EmbeddedICE
WDATA
-RT
Interface
ARM9EJ-S
ETM
The ARM9EJ-S processor can operate in three different states, each with a specific instruction
set:
In Jazelle state, all instruction Fetches are in words.
The operating state of the ARM9EJ-S core can be switched between:
• ARM state: 32-bit, word-aligned ARM instructions.
• THUMB state: 16-bit, halfword-aligned Thumb instructions.
• Jazelle state: variable length, byte-aligned Jazelle instructions.
• ARM state and THUMB state using the BX and BLX instructions, and loads to the PC
Processor
RDATA
INSTR
Coprocessor
DA
Interface
IA
Droute
Iroute
ARM926EJ-S
DCACHE
DEXT
MMU
ICACHE
IEXT
Interface
Interface
TCM
Instruction
Bus
Unit
Interface
Interface
AHB
Data
AHB
AHB
AHB
6062N–ATARM–3-Oct-11