RM9200 Atmel Corporation, RM9200 Datasheet - Page 84
RM9200
Manufacturer Part Number
RM9200
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.RM9200.pdf
(350 pages)
4.RM9200.pdf
(149 pages)
5.RM9200.pdf
(41 pages)
6.RM9200.pdf
(701 pages)
Specifications of RM9200
Flash (kbytes)
0 Kbytes
Pin Count
256
Max. Operating Frequency
180 MHz
Cpu
ARM920
Hardware Qtouch Acquisition
No
Max I/o Pins
122
Ext Interrupts
122
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
1
Twi (i2c)
1
Uart
5
Ssc
3
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- RM9200 PDF datasheet #3
- RM9200 PDF datasheet #4
- RM9200 PDF datasheet #5
- RM9200 PDF datasheet #6
- Current page: 84 of 284
- Download datasheet (2Mb)
Memory Interface
3.5
3-14
Address timing
The ARM7TDMI processor address bus can operate in one of two configurations:
•
•
ARM Limited strongly recommends that pipelined address timing is used in new design
to obtain optimum system performance.
ARM Limited strongly recommends that ALE is tied HIGH and not used in new
designs.
Address depipelined configuration is controlled by the APE or ALE input signal. The
configuration is provided to ease the design of the ARM7TDMI processor in both
SRAM and DRAM-based systems.
APE affects the timing of the address bus A[31:0], plus nRW, MAS[1:0], LOCK,
nOPC, and nTRANS.
In most systems, particularly a DRAM-based system, it is desirable to obtain the
address from ARM7TDMI processor as early as possible. When APE is HIGH then the
ARM7TDMI processor address becomes valid after the rising edge of MCLK before
the memory cycle to which it refers. This timing allows longer periods for address
decoding and the generation of DRAM control signals. Figure 3-8 shows the effect on
the timing when APE is HIGH.
SRAMs and ROMs require that the address is held stable throughout the memory cycle.
In a system containing SRAM and ROM only, APE can be tied permanently LOW,
producing the desired address timing. In this configuration the address becomes valid
after the falling edge of MCLK as shown in Figure 3-9 on page 3-15.
nMREQ
D[31:0]
A[31:0]
MCLK
pipelined
depipelined.
SEQ
APE
Note
Copyright © 1994-2001. All rights reserved.
Figure 3-8 Pipelined addresses
ARM DDI 0029G
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