RM9200 Atmel Corporation, RM9200 Datasheet - Page 127
RM9200
Manufacturer Part Number
RM9200
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.RM9200.pdf
(350 pages)
4.RM9200.pdf
(149 pages)
5.RM9200.pdf
(41 pages)
6.RM9200.pdf
(701 pages)
Specifications of RM9200
Flash (kbytes)
0 Kbytes
Pin Count
256
Max. Operating Frequency
180 MHz
Cpu
ARM920
Hardware Qtouch Acquisition
No
Max I/o Pins
122
Ext Interrupts
122
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
1
Twi (i2c)
1
Uart
5
Ssc
3
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- RM9200 PDF datasheet #3
- RM9200 PDF datasheet #4
- RM9200 PDF datasheet #5
- RM9200 PDF datasheet #6
- Current page: 127 of 284
- Download datasheet (2Mb)
5.2.3
ARM DDI 0029G
Debug target
The ARM7TDMI processor has hardware extensions that ease debugging at the lowest
level. The debug extensions:
•
•
•
•
The major blocks of the debug target are shown in Figure 5-2.
The ARM CPU core
The EmbeddedICE Logic
The TAP controller
allow you to halt program execution
examine and modify the core internal state of the core
view and modify the state of the memory system
resume program execution.
Copyright © 1994-2001. All rights reserved.
EmbeddedICE
This has hardware support for debug.
This is a set of registers and comparators used to generate debug
exceptions such as breakpoints. This unit is described in About
EmbeddedICE Logic on page 5-13.
This controls the action of the scan chains using a JTAG serial interface.
Scan chain 2
Logic
TAP controller
Scan chain 0
Scan chain 1
Figure 5-2 ARM7TDMI block diagram
Main processor
logic
Debug Interface
5-5
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