RM9200 Atmel Corporation, RM9200 Datasheet - Page 74

• Manufacturer Part Number: RM9200
• Manufacturer: Atmel Corporation

Specifications of RM9200

• Flash (kbytes): 0 Kbytes
• Pin Count: 256
• Max. Operating Frequency: 180 MHz
• Cpu: ARM920
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 122
• Ext Interrupts: 122
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 1
• Twi (i2c): 1
• Uart: 5
• Ssc: 3
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Memory Interface
3.3
3-4
Bus cycle types
The ARM7TDMI processor bus interface is pipelined. This gives the maximum time for
a memory cycle to decode the address and respond to the access request:
•
•
A single memory cycle is shown in Figure 3-1.
The ARM7TDMI processor bus interface can perform four different types of bus cycle:
•
•
•
•
memory request signals are broadcast in the bus cycle ahead of the bus cycle to
which they refer
address class signals are broadcast half a clock cycle ahead of the bus cycle to
which they refer.
a nonsequential cycle requests a transfer to or from an address which is unrelated
to the address used in the preceding cycle
a sequential cycle requests a transfer to or from an address which is either the
same, one word, or one halfword greater than the address used in the preceding
cycle
an internal cycle does not require a transfer because it is performing an internal
function, and no useful prefetching can be performed at the same time
a coprocessor register transfer cycle uses the data bus to communicate with a
coprocessor, but does not require any action by the memory system.
Copyright © 1994-2001. All rights reserved.
nMREQ
D[31:0]
A[31:0]
MCLK
SEQ
APE
Figure 3-1 Simple memory cycle
ARM DDI 0029G