M55800A Atmel Corporation, M55800A Datasheet - Page 79

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

3.3.5
ARM DDI 0029G
Coprocessor register transfer cycles
When designing a memory controller, ensure that the design also works when an I-cycle
is followed by an N-cycle to a different address. This sequence can occur during
exceptions, or during writes to the PC. It is essential that the memory controller does
not commit to the memory cycle during an I-cycle.
During a coprocessor register transfer cycle, the ARM7TDMI processor uses the data
buses to transfer data to or from a coprocessor. A memory cycle is not required and the
memory controller does not initiate a transaction. The memory system must not drive
onto the data bus during a coprocessor register transfer cycle.
The coprocessor interface is described in Chapter 4 Coprocessor Interface. The
coprocessor register transfer cycle is shown in Figure 3-6 on page 3-10.
Note
Copyright © 1994-2001. All rights reserved.
nMREQ
A[31:0]
D[31:0]
MCLK
nRAS
nCAS
SEQ
I-cycle
Figure 3-5 Merged IS cycle
S-cycle
Memory Interface
3-9