M55800A Atmel Corporation, M55800A Datasheet - Page 275

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Glossary
Abort
Addressing modes
Arithmetic Logic Unit
ALU
ARM state
Big-endian
Banked registers
ARM DDI 0029G
This glossary describes some of the terms used in this manual. Where terms can have
several meanings, the meaning presented here is intended.
Is caused by an illegal memory access. Abort can be caused by the external memory
system, an external MMU or the EmbeddedICE Logic.
A procedure shared by many different instructions, for generating values used by the
instructions. For four of the ARM addressing modes, the values generated are memory
addresses (which is the traditional role of an addressing mode). A fifth addressing mode
generates values to be used as operands by data-processing instructions.
The part of a computer that performs all arithmetic computations, such as addition and
multiplication, and all comparison operations.
See Arithmetic Logic Unit.
A processor that is executing ARM (32-bit) instructions is operating in ARM state.
Memory organization where the least significant byte of a word is at a higher address
than the most significant byte.
Register numbers whose physical register is defined by the current processor mode. The
banked registers are registers R8 to R14.
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Glossary-1